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Self-testing method and apparatus for synchronous dynamic random memory

A random access memory, synchronous dynamic technology, applied in the direction of instruments, error detection/correction, electrical digital data processing, etc., can solve SDRAM SDRAM controller failure, timing difficult to meet the requirements, data path paralysis and other problems, to increase maintainability, The effect of increasing complexity and increasing reliability

Inactive Publication Date: 2004-06-16
HUAWEI TECH CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] Due to various harsh environments that may be encountered in actual working conditions, it may cause failure of the SDRAM or the read-write arbitration module and SDRAM controller that control the SDRAM. Once this happens, the entire flow control unit (referred to as : flow control unit) data path paralysis
[0004] In addition, the SDRAM part belongs to the 100M clock domain in the system, and the timing is difficult to meet the requirements, which is a weak link in the system. Therefore, it needs to be remedied in some way

Method used

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  • Self-testing method and apparatus for synchronous dynamic random memory
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  • Self-testing method and apparatus for synchronous dynamic random memory

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Embodiment Construction

[0019] The present invention embeds an SDRAM self-test module in the module of the flow control unit to realize normal business. The CPU performs self-test on the SDRAM at the beginning of power-on. There is no mutual influence between the self-test state and the normal working state, which can greatly increase the reliability and testability of the SDRAM part.

[0020] Such as figure 1 As shown, the SDRAM self-test module 11 is embedded in the system flow control unit, and is connected with the CPU 12 and the read-write arbitration module 13 respectively, and is also connected with the data input / output ports 14 and 15. It includes a first dual-port RAM1 and a second dual-port RAM1. Port RAM2 and its read and write control logic, others also include the switching switch between the entrance fifo, the exit fifo and the dual-port RAM.

[0021] When the system is in the normal working mode, that is, when the business is normally transmitted, the SDRAM self-test module 11 is shi...

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Abstract

A method and apparatus for performing self-test to synchronized dynamic random access memory, wherein the method comprises, starting self-test to synchronized dynamic random access memory SDRAM, switching the system to self-test mode, the CPU writing data to the first pair port RAM of the self-test module, the arbitration module reading data from the first pair port RAM and writing into SDRAM, the arbitration module reading back data from SDRAM and writing into the second pair port RAM of the self-test module, the CPU comparing the write-in and read-out data for determining whether SDRAM is operating normally. The invention increases the system reliability and maintainability.

Description

technical field [0001] The invention relates to a method for buffering data input from a media access control MAC layer by a synchronous dynamic random access memory SDRAM (Synchorous DRAM) to achieve reliable flow control in the process of Ethernet transparent transmission of a synchronous digital system SDH. Background technique [0002] In the process of realizing Ethernet transparent transmission SDH, SDRAM is required to cache the data input from the MAC layer to realize flow control. SDRAM is a dynamic random access memory DRAM that completes data reading and writing under the control of an external synchronous clock. Like ordinary DRAM, it needs periodic refreshing operation, and the row address must be given before the access, and then the column address must be given. However, the input signals of SDRAM are latched with the rising edge of the system clock, so that the device can operate completely synchronously with the system clock. It embeds a synchronous contro...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/00
Inventor 徐春石磊
Owner HUAWEI TECH CO LTD
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