Method and apparatus for reducing phase jitter in clock recovery system

Abstract

The invention provides a method to reduce phase shake in clock recovering system and the equipment. The clock recovering system has a phase detector to detect the phase difference between an input signal and a clock signal output by a voltage controlled oscillator, generates a rising pulse and a descending pulse according to the phase difference, and uses the two pulses to generate a control voltage of the voltage controlled oscillator. It uses a time delay component to make the two pulses overlap in the time field, to eliminate the ripple generated on the control voltage, so as to prevent the clock signal from producing phase shake.

Description

technical field [0001] The invention relates to a method and device for reducing phase jitter in a clock recovery system, in particular to a method that can eliminate the ripple on the control voltage of a voltage-controlled oscillator to avoid phase jitter caused by too fast changes of the voltage-controlled oscillator method and device. Background technique [0002] Phase Locked Loop (Phase Locked Loop) is commonly used as frequency control, which can generally be used as frequency multiplier (Multiplier), demodulator (Demodulator), track tracking generator (Tracking Generator), clock recovery system (Clock Recovery Circuit) and other applications. Recently, there are optical disc media with high reproduction rate, such as CD-ROM, DVD, etc., and a clock recovery system is used to perform synchronous regeneration of data. Such as figure 1 As shown, a typical clock recovery system 1 includes a phase detector 11 , a charge extractor 12 , a loop filter 13 , a voltage contro...

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Problems solved by technology

[0003] However, if figure 2 As shown, since the typical phase detector 11 will first output the rising pulse UP, and then output the falling pulse DN, that is, the rising pulse UP and the falling pulse DN are not output at the same time. The control voltage V ct With the sequential appearance of rising pulse UP and falling pulse DN, it gradually integrates, so that the control voltage V ct In addition to the voltage ΔV actually generated by the phase difference Δt, there is also an unwanted ripple (ripple) V r , and these ripples V r Even a small phase difference will occur, which will not only drive the voltage-controlled oscillator 14 to continuously change the phase of the clock signal CLK, causing the phase jitter of the clock signal CLK, but also causing the frequency of the clock signal CLK to rise or The drop is too fast, so that when the clock signal CLK is used to sample the input signal DATA, the data judgment error will be caused by the offset of the sampling point, and the phase of these up and down jitters will appear with the transition edge of the input signal (data) DATA Corresponding ripples are generated by the frequency, which will cause data-dependent jitter (data dependent jitter)

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