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Selective memory refreshing circuit and method

A memory, selective technology, applied in static memory, digital memory information, information storage, etc., can solve the problems of long refresh time, short standby time, power waste and so on

Inactive Publication Date: 2007-03-07
UNITED MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, the entire refresh time will be longer, and at the same time refreshing the word lines that do not store data will also cause the main source of current consumption
[0004] With the popularity of personal and portable electronic devices and the increase in memory capacity, excessive current consumption will cause power waste, making the standby time of mobile and portable electronic devices short, because the power is consumed by refreshing the memory

Method used

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  • Selective memory refreshing circuit and method

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Embodiment Construction

[0025] The main focus of the present invention is to configure a latch that can memorize the word line address for each bit line (connected to the gate of the memory cell transistor) in a memory array, and use this latch to judge its corresponding word line Whether the online storage unit is used to store data. When the word line has memory to store data, the word line will be refreshed during the refresh cycle; on the contrary, if the word line has no memory to store data, the word line will not be refreshed during the refresh cycle operate. Therefore, the refresh operation can be accelerated and can have power saving effects.

[0026] In addition, the present invention can cooperate with the release command controller, the word line refresh comparator and the local sense amplifier (local sense amplifier) ​​circuit to complete the refresh circuit and method of the present invention.

[0027] First, FIG. 1 is a block diagram showing a word line address latch of the present i...

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Abstract

The selective memory refreshing circuit is used in refreshing memory array with several digital byte lines connected to the byte refreshing selective circuit, which is used to judge whether these byte lines have in refreshment. Each byte refreshing selective circuit includes also byte line address latch for accepting byte line predecoding signal, release signal and start signal and outputting byte line latching signal; and byte line refreshing comparator circuit for comparing the byte line predecoding signal and the byte line latching signal and transmitting the result to the byte line driver. If the byte line latching signal is high level, the byte line will be refreshed.

Description

technical field [0001] The present invention relates to a memory refreshing circuit and refreshing method, and in particular to a circuit and method capable of refreshing only memory cells on word lines with stored data. Background technique [0002] A general dynamic random access memory (DRAM) is composed of a transistor and a capacitor. Use the charge stored in the capacitor to achieve different storage states, such as "1" and "0". However, over time, the charge stored in the capacitor is lost due to leakage, causing its holding voltage to drop. Therefore, it is difficult to distinguish its storage state. For this reason, a refresh cycle is required to charge the capacitance of the storage unit for a long time. When refreshing, there will be current consumption, resulting in power loss. [0003] In the current memory refresh method, all word lines are refreshed, regardless of whether the memory cells on the word lines have stored data or not....

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/406
Inventor 陈瑞隆黄世煌
Owner UNITED MICROELECTRONICS CORP
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