Systems and method for retaining circuit in phase locked loop

Abstract

Improved phase locked loops are described which handle momentary breaks in an input communication channel. The phase locked loops provide the capability to "hold" the output clock in a communication system at or very near the last output frequency before the loss of input data. Such phase locked loops include a differential phase detector, an electronic selector circuit, and an operational amplifier based loop filter circuit. The electronic selector circuit provides the differential output of the phase detector at a pair of inputs to the operational amplifier. A voltage controlled oscillator is coupled to an output of the operational amplifier and provides an output frequency for the phased locked loop circuit. The electronic selector circuit is operable to control the input to the operational amplifier to hold an output frequency of the voltage controlled oscillator at a substantially constant frequency.

Description

technical field [0001] The present invention relates generally to the field of telecommunications and, more particularly, to systems and methods for holdover circuits in phase locked loops. Background technique [0002] The increasing popularity of new communication systems, such as the Internet, has created a need for network systems that provide greater and greater bandwidth and data control facilities. Prior to the rapid proliferation of the Internet, most telecommunications systems were designed with architectures that primarily supported a single service, such as voice calls. Today's newer telecommunications systems must be designed for greater bandwidth demands and data control devices. These newer systems and networks must be able to provide two-way simultaneous transmission of video, audio and other data. [0003] Phase-locked loops are often used in two-way data communication systems to generate an output clock derived from input data. Generally, a phase-locked l...

AI Technical Summary

Problems solved by technology

The problem with this prior art approach is that the fixed voltage reference of the alternative voltage controlled oscillator can be, and often is, significantly different from the clock frequency to which the phase-locked loop locked just before the loss of input data

In this case, the system still suffers from significant problems where rapid switching from one clock frequency to another results in data errors

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