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Memory controller for improving data integrity and operation method thereof

A memory controller and data integrity technology, applied in random number generators, digital data protection, electrical digital data processing, etc., can solve problems such as signal integrity issues, undisclosed modular ECC implementation methods, etc.

Pending Publication Date: 2022-08-09
SKYECHIP SDN BHD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Seeding only memory addresses for scrambling / descrambling will produce predictable data patterns that can cause signal integrity issues due to resonance
Furthermore, none of the memory controllers in the aforementioned references disclose a modular ECC implementation capable of supporting any DRAM interface width or protocol

Method used

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  • Memory controller for improving data integrity and operation method thereof
  • Memory controller for improving data integrity and operation method thereof
  • Memory controller for improving data integrity and operation method thereof

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0041] According to a first embodiment of the method of operating a memory controller (100), the method further comprises the step of: encoding the scrambled data by an error correction code encoding component (8) before transferring the scrambled data to the memory device (2) to encode.

[0042] According to a first embodiment of the method of operating a memory controller (100), the method further comprises the steps of: receiving read data from the memory device (2) in a receive data path; Decoding the data; dividing the read data into a first part and a second part; based on the first part of the read data and a fixed seed corresponding to the first part of the read data, generating an output through a first XOR logic (14) ; According to the output and the address associated with the read data, a pseudo-random output is generated by the descrambling logic (16); by the second XOR logic (14), in response to the pseudo-random output, a second portion of the read data is perfo...

no. 2 example

[0044]According to a second embodiment of the method of operating a memory controller (100), the method further comprises the steps of: receiving read data from the memory device (2) in a receive data path; dividing the read data into a first part and a second part part; based on the first part of the read data and a fixed seed corresponding to the first part of the read data, an output is generated by a first XOR logic (14); based on the output and the address associated with the read data, by descrambling Logic (16) generates a pseudo-random output; by second XOR logic (14), descrambling the second portion of the read data in response to the pseudo-random output, and in response to a fixed corresponding to the first portion of the read data seed, descramble the first part of the read data, thereby generating descrambled data; and decode the descrambled data by an error correction code decoding component (10).

[0045] The memory controller (100) described above overcomes the...

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Abstract

The invention relates to a memory controller (100) for improving data integrity and providing data security. The memory controller (100) comprises a transmission data path for transmitting write data to the memory device (2); the transmission data path comprises a scrambling component (4); the scrambling component (4) comprises scrambling logic (12) and exclusive OR logic (14); the write-in data is divided into a first part and a second part; the input of the scrambling logic (12) includes a first portion of the write data and an address associated with the write data to generate a pseudo-random output; the input of the exclusive OR logic (14) includes a second portion of the write data, a pseudo-random output, and a fixed seed corresponding to the first portion of the write data to generate scrambled data. In addition, the invention also relates to a method for operating the memory controller (100).

Description

technical field [0001] The present invention generally relates to a memory controller for improving data integrity and providing data security, and in particular to a memory controller equipped with an error correction code (ECC) implementation and a data scrambling / descrambling implementation . The invention also relates to a method of operating a memory controller. Background technique [0002] Memory devices, such as dynamic random access memory (DRAM), store electronic data, while memory controllers manage the flow of electronic data to and from the memory devices. For write data, some memory controllers scramble the electronic data and encode the scrambled data before storing the electronic data in the memory device. Among them, scrambling can be used to improve the signal-to-noise ratio on the DRAM interface, and coding can be used to perform error correction coding or data recovery. [0003] Reading the stored data involves decoding the stored data and descrambling...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/10G06F7/58G06F21/62G06F21/64
CPCG06F11/1048G06F7/584G06F21/6218G06F21/64G06F13/1668G06F11/1052G06F21/78G06F21/602G06F11/1076
Inventor 王育颖穆罕默德·艾迪尔·本·贾兹米林舜杰郑誌学
Owner SKYECHIP SDN BHD
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