Eureka AIR delivers breakthrough ideas for toughest innovation challenges, trusted by R&D personnel around the world.

Capacitance-free DRAM (Dynamic Random Access Memory) unit structure and manufacturing method

A technology of cell structure and manufacturing method, which is applied in electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve the problems of large occupied area and low integration density, so as to reduce process manufacturing costs, improve integration, and reduce unit area. Effect

Pending Publication Date: 2022-08-05
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
View PDF0 Cites 3 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the existing 2T0C DRAM cells based on IGZO TFT generally use two horizontal channel TFTs connected on the same plane, occupying a large area and low integration density

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Capacitance-free DRAM (Dynamic Random Access Memory) unit structure and manufacturing method
  • Capacitance-free DRAM (Dynamic Random Access Memory) unit structure and manufacturing method
  • Capacitance-free DRAM (Dynamic Random Access Memory) unit structure and manufacturing method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0031] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.

[0032] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The figures are not to scale, some details have been exaggerated for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships are only exemplary, and may vary in practice due to manufacturing tolerances or technical limitations, and those skilled in the art will Regions / layers with differen...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention relates to a capacitance-free DRAM (Dynamic Random Access Memory) unit structure and a manufacturing method. The capacitance-free DRAM unit structure comprises a semiconductor substrate, a first isolation layer, a lower source-drain layer, a lower active region, a lower gate dielectric layer, a lower gate electrode layer, a second isolation layer, an upper source-drain layer, an upper active region layer, an upper gate dielectric layer and an upper gate electrode layer which are sequentially stacked from bottom to top, the lower source drain layer comprises a lower source electrode and a lower drain electrode which are separated by a first groove, and the bottom of the first groove is in contact with the first isolation layer; the upper source drain layer comprises an upper source electrode and an upper drain electrode which are separated by a second groove, and the bottom of the second groove is in contact with the second isolation layer; the lower gate electrode layer and the upper source drain layer are electrically connected through a contact hole arranged in the second isolation layer. According to the DRAM unit structure, the upper transistor and the lower transistor are completely overlapped, the unit area is saved, the integration density is improved, multiplexing of a gate electrode photoetching plate can be achieved, and the manufacturing cost is reduced.

Description

technical field [0001] The present invention relates to the field of transistors, in particular to a structure and a manufacturing method of a capacitorless DRAM cell. Background technique [0002] The traditional DRAM (Dynamic Random Access Memory) unit consists of a transistor and a capacitor, but with the increase of integration, the capacitor structure continues to shrink, the charge storage continues to decrease, the leakage is too fast, and the DRAM is about to reach the refresh frequency limit. . [0003] Therefore, two oxide semiconductors IGZO (Indium Gallium Zinc Oxide InGaZnO 4 ) 2T0C (2transistor 0capacitor dual transistor no capacitor) DRAM cell with thin film transistor, such as figure 1 As shown, the drain of one transistor is connected to the gate of the other transistor, using the gate capacitance to store charge and changing the transistor transconductance to store information. [0004] In recent years, 2T0C memories with indium gallium zinc oxide (Indiu...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/108H01L21/8242H10B12/00
CPCH10B12/01H10B12/00
Inventor 杨尚博许高博殷华湘罗军
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Eureka Blog
Learn More
PatSnap group products