Interface design and communication method for extensible interconnection bare core and peer-to-peer device

Abstract

The invention provides a network interface design and communication method for an extensible interconnection bare core and peer-to-peer equipment, the network interface NI facing the peer-to-peer equipment is composed of a protocol converter and an event controller, and the protocol converter comprises a Shell, a Buffer and a Kerne. The Shell is a local bus protocol controller and can complete format conversion and data receiving and transmitting according to a peer-to-peer device interface bus format and a data packet transmission data format; the Buffer is used for data buffering and clock domain isolation; the Kernel is mainly used for completing data packing and unpacking work; the event controller is mainly used for managing and organizing request and response events, ensuring one-to-one correspondence between requests and responses, and avoiding loss of data packets. Meanwhile, the invention provides an interface design scheme based on an Initiator / Target mode and a CondensedI / O mode, and expansion of the peer-to-peer equipment in the high-performance information processing microsystem and high-speed communication between the peer-to-peer equipment and the interconnection bare core can be realized by interconnecting the peer-to-peer interface provided by the interconnection bare core and the peer-to-peer interface of the peer-to-peer equipment.

Description

technical field [0001] The present invention relates to a communication method between a bare core and a peer device, in particular to an interface design and a communication method for extensible interconnection of the bare core and the peer device. Background technique [0002] In a monolithic ASIC, all components are designed and fabricated on a single silicon wafer using the same process. As process dimensions shrink, the cost and development cycle to develop a monolithic ASIC becomes extremely high. In this case, multi-die integration is an inevitable choice for the development of high-performance chips in the future, that is, multiple chip components with different functions that have been verified and unpackaged are interconnected and assembled, and packaged as chips in the same package As a whole, a package-level network NoP (Network on Package) is formed. These bare cores can use different processes and come from different manufacturers, thus greatly shortening an...

AI Technical Summary

Problems solved by technology

The existing communication protocols for multi-core integration are either dedicated protocols with poor versatility; or the technical system is too complex and difficult to use

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