Nested delay lock ring

Abstract

The invention discloses a nested delay locked loop, which belongs to the technical field of chip design, and comprises two mutually nested delay locked loops (DLL) in a chip circuit loop, the first delay locked loop (DLL1) can synchronize the output of a digital-to-analog converter (DAC) with an input differential clock (CLKP and CLKN), the second delay locked loop (DLL2) can generate a clock with the same frequency as the input differential clock (CLKN), and the first delay locked loop (DLL1) and the second delay locked loop (DLL2) can generate a clock with the same frequency as the input differential clock (CLKN). Therefore, the total delay of a chip circuit loop system clock or a signal path is minimized; according to the invention, the two delay locked loops (DLL) in the loop of the chip circuit are nested with each other, so that the synchronization requirements of respective loop clocks and signals are met, and the design goal of minimizing the total delay of the loop system of the chip circuit is achieved.

Description

technical field [0001] The invention belongs to the technical field of chip design, and in particular relates to a nested delay locked ring. Background technique [0002] In fields such as wired communication and large-scale digital circuits, clock synchronization and delay control are very important and difficult specialized techniques. With the continuous improvement of communication speed and digital processor frequency, especially when it involves signal and clock loops formed between different chips, the delay control of synchronous communication or digital calculation becomes more complex and challenging. [0003] As an application example of the present invention, while generating a multi-phase clock required by a digital-to-analog converter (DAC: digital-to-analog converter), it is also required that the DAC output is synchronized with the off-chip input clock. The problem often encountered in the design of similar chips is: when using multiple independent delay loc...

AI Technical Summary

Problems solved by technology

The problem often encountered in the design of similar chips is: when using multiple independent delay locked loops (DLL: delay locked loop) to meet the system's synchronization requirements for clocks and signals, it increases the total number of clock or signal paths. time delay

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