Pipeline level arithmetic device and pipeline analog-to-digital converter

Abstract

The invention discloses a pipeline level operation device and a pipeline analog-to-digital converter. The pipeline level operation device comprises a dynamic matching sub-analog-to-digital converter, a sampling holder, a pseudo-random code generator and a multiplication digital-to-analog converter, wherein the multiplication digital-to-analog converter is respectively connected with the dynamic matching sub-analog-to-digital converter and the sampling holder, and the dynamic matching sub-analog-to-digital converter is connected with the pseudo-random code generator. Based on the dynamic matching sub-analog-to-digital converter, the threshold voltages of comparators can be changed by using pseudo-random codes, and the dynamic matching of the comparators is realized, so the dynamic matching of a capacitor array in the sub-analog-to-digital converter in the multiplication digital-to-analog converter is realized, and capacitor mismatching caused by process errors, manufacturing processes and the like is scattered. As the threshold voltages of the comparators only need to be prepared before comparison of the comparators, the dynamic matching technology of the threshold voltages can be applied to the retention period of the whole analog-to-digital conversion, and on the basis of not occupying the analog-to-digital conversion time, harmonic distortion is reduced and the linearity of the analog-to-digital converter is improved.

Description

technical field [0001] The present application relates to the technical field of analog-to-digital converters, and in particular to a pipeline-level computing device and a pipelined analog-to-digital converter. Background technique [0002] Pipelined ADC has become one of the most widely used analog-to-digital converters due to its advantages such as high precision, fast conversion speed, and low power consumption. In the signal processing process, the analog signal Vin enters the sample-and-hold circuit and is initially quantized and then directly enters the first pipeline stage. The first pipeline stage quantizes the signal into an N bit digital code, and outputs the analog residual voltage to enter the next stage. The pipeline stage (second pipeline stage) performs the same processing. In order to realize high-speed pipeline operation, the pipeline analog-to-digital converter performs sampling at the moment when the previous stage is held, and holds at the moment when th...

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Problems solved by technology

[0004] In the pipeline ADC, the capacitance mismatch error in MDAC is one of the main nonlinear sources of the whole system, which will lead to the inter-stage gain error and the inconsistency of the jump height of the input and output curves of the stage circuit, making the analog-to-digital converter Poor linearity and reduced accuracy of analog-to-digital conversion

In existing methods, in order to realize high-precision pipelined analog-to-digital converters, the traditional structure usually adopts adding pseudo-random codes and Dynamic ElementL Matching (Dynamic ElementL Matching, DEM) to the encoding circuit of the subDAC in each stage of MDAC. technology, that is, the capacitor array in MDAC is rearranged according to the random control signal at each hold clock, but this method must add a logic switch control circuit module in front of the capacitor array, which not only leads to the circuit The bandwidth is reduced, and it needs to occupy the already tight sample and hold time, which leads to the inability to balance the high precision and high speed of the analog-to-digital conversion process, and is not suitable for the design of high-speed analog-to-digital converters

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