ESD protection device for fully-depleted silicon-on-insulator and preparation method of ESD protection device

Abstract

The invention provides an ESD protection device for a fully-depleted silicon-on-insulator and a preparation method of the ESD protection device. The device comprises bottom layer silicon which has P-type low doping, a buried oxide layer which is formed on the bottom layer silicon, a top layer silicon which is formed on the buried oxide layer and has P-type low doping, a first N-type heavily doped region which is formed in the top layer silicon, a second N-type heavily doped region which is formed in the top layer silicon, a P-type heavily doped region which is formed on the top layer silicon between the first N-type heavily doped region and the second N-type heavily doped region, a first base electrode which is electrically connected with the first N-type heavily doped region, a second base electrode which is electrically connected with the second N-type heavily doped region, an emitter electrode which is electrically connected with the P-type heavily doped region, and a gate electrode which is electrically connected with the bottom layer silicon. According to the ESD protection device, the unijunction transistor is used for forming a voltage stabilization structure, high-voltage ESD protection is achieved, and the ESD protection device is suitable for the fully-depleted silicon-on-insulator.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to a fully depleted silicon-on-insulator ESD protection device and a preparation method thereof. Background technique [0002] As microelectronic devices are shrinking in size and integrating functions, electrostatic protection (Electrostatic discharge, ESD) of chips is becoming more and more important. First of all, the gate dielectric and isolation of small-sized devices are thinner, which leads to the weakening of the device's ability to withstand static electricity, thus narrowing the window for ESD device design. Second, more and more modules are integrated on the same silicon substrate, resulting in more and more risks for chips to suffer from ESD. In addition, silicon-on-insulator (SOI) devices, especially fully depleted silicon-on-insulator (FDSOI) devices, have thin top layers, making it difficult to prepare high-voltage ESD protection devices. [0003] Therefore, how t...

AI Technical Summary

Problems solved by technology

First of all, the gate dielectric and isolation of small-sized devices are thinner, which leads to the weakening of the device's ability to withstand static electricity, thus narrowing the window for ESD device design

Second, more and more modules are integrated on the same silicon substrate, resulting in more and more risks for chips to suffer from ESD

In addition, silicon-on-insulator (SOI) devices, especially fully depleted silicon-on-insulator (FDSOI) devices, have thin top layers, making it difficult to prepare high-voltage ESD protection devices

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