Cavity detection method for 3D NAND memory

Abstract

The invention provides a cavity detection method for a 3D NAND memory. The cavity detection method comprises the following steps: removing a part, located on a plurality of stacked structures arranged at intervals, of a filling layer; removing the second sacrificial layers and the parts, between the adjacent second sacrificial layers, of the filling layer; removing the second insulating layers and the parts, located between the adjacent second insulating layers, of the filling layer; forming a protection layer covering the side wall and the bottom of the substrate; and processing the 3D NAND memory by using a first wet etching process and carrying out cavity detection. According to the void detection method provided by the invention, the filling layer is partially removed to expose the top surface of the part, between the adjacent first sacrificial layers, of the filling layer, and then the substrate is processed by using the first wet etching process. Whether the filling layer has a hole is determined by detecting whether the substrate has an etching trace, so that the 3D NAND memory is prevented from generating electric leakage abnormity.

Description

technical field [0001] The present application relates to the technical field of memory manufacturing, in particular to a method for detecting voids in 3D NAND memory. Background technique [0002] NAND flash memory is a better storage device than hard disk drives, and it has been widely used in electronic products as people pursue non-volatile storage products with low power consumption, light weight and high performance. At present, the planar NAND flash memory is close to the limit of practical expansion. In order to further increase the storage capacity and reduce the storage cost per bit, a 3D NAND memory is proposed. [0003] At present, the manufacturing process of 3D NAND memory includes: forming a stack layer composed of insulating layers and sacrificial layers alternately stacked on the substrate; trimming and etching the stack layer to form a stack of multiple intervals in a stepped shape structure; forming a filling layer, and the filling layer fills the space a...

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Problems solved by technology

[0004] Wherein, during the process of forming the filling layer, a void may be formed in the filling layer, and after removing the sacrificial layer and filling the conductive material to form the gate, the void will make the bottom selective gate (BSG) communicate with the substrate, And cause abnormalities such as leakage, which in turn affects the product yield and production efficiency of 3D NAND memory

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