Compact power divider chip based on folded coil

Abstract

The invention provides a compact power divider chip based on a folded coil. The compact power divider chip comprises the folded coil, an RC series network and two resonant capacitors, wherein the folded coil comprises a first-stage coupling coil and a second-stage coupling coil which are connected; the first-stage coupling coil is formed by mutually winding two inductors which are completely symmetrical up and down, and a coil tap of the first-stage coupling coil is connected with a combining port of the power divider chip; the second-stage coupling coil is formed by mutually winding two inductors which are completely symmetrical up and down; the second-stage coupling coil is folded into the first-stage coupling coil; the RC series network is arranged in the first-stage coupling coil and comprises a first-stage RC series network and a second-stage RC series network; the first-stage RC series network is connected with two power division paths of the first-stage coupling coil; the second-stage RC series network is connected with two power division paths of the second-stage coupling coil; and the two resonant capacitors are connected to the joint of the first-stage coupling coil and the second-stage coupling coil and are connected to the ground. According to the compact power divider chip, the size of the power divider chip can be greatly reduced, and excellent performance is shown.

Description

technical field [0001] The invention relates to the field of microwave radio frequency integrated circuits, in particular to a compact power divider chip based on a folded coil. Background technique [0002] The operating bandwidth is an important indicator of the power divider, which is defined as the operating frequency range where the indicators of interest all meet the operating conditions. The bandwidth of the power divider is usually measured by the relative bandwidth coefficient B, which is defined as: [0003] [0004] where f h High-end cutoff frequency for power divider operation, f l Low-end cutoff frequency for power divider operation. [0005] The chip area is directly related to the cost of the chip and the integration of the upper-layer system, and is an important concern of the chip. [0006] In the existing one-to-two power divider products, for the power divider with k<1.5, in order to reduce the layout area, the lumped parameter design is usually...

AI Technical Summary

Problems solved by technology

[0007] The present invention aims to provide a compact power divider chip based on folded coils to solve the problem of excessive chip area

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