Parallel simulation processing method of gate-level circuit and computer readable storage medium

Abstract

The invention discloses a parallel simulation processing method of a gate-level circuit and a computer readable storage medium. The parallel simulation processing method of the gate-level circuit comprises the following steps: based on an adjacent matrix of the gate-level circuit, segmenting a graph corresponding to the gate-level circuit into a plurality of clusters by adopting a first preset segmentation algorithm; taking each cluster as a superpoint, and packaging data of each superpoint by adopting a first data structure; on the basis of a superpoint diagram formed by all the superpoints, dividing all the superpoints into a plurality of partitions capable of being processed in parallel by adopting a second preset segmentation algorithm, and packaging partition data by adopting a second data structure; generating a cluster priority event queue between clusters and a node priority event queue in the clusters by adopting a preset priority distribution algorithm on the basis of the super-point data and the partition data; and simulating the gate-level circuit according to a simulation sequence defined by the priority event queue. According to the invention, the simulation efficiency of the gate-level circuit can be effectively improved, and the simulation complexity of the gate-level circuit is reduced.

Description

technical field [0001] The invention relates to the technical field of gate-level circuit simulation, in particular to a parallel simulation processing method capable of improving gate-level circuit simulation efficiency. Background technique [0002] With the continuous development of integrated circuits, whether it is chip forward design or reverse design, they are more and more dependent on tools, which poses a higher challenge to the processing speed of related software. Completely free and open source digital chip simulators include Icarus Verilog, Yosys, etc. [0003] In the simulation process, due to the influence of the circuit design scale, the simulation time of circuits of different scales varies greatly. Large-scale circuit simulation takes a very long time, while for small-scale circuit simulation it takes microseconds. Accelerated circuit simulation is a chip Key issues that need to be effectively resolved in the simulation stage. The running speed of most so...

AI Technical Summary

Problems solved by technology

[0005] In order to solve the technical problem of high hardware cost caused by high-performance hardware for simulation acceleration in the prior art, the present invention proposes a parallel simulation processing method for gate-level circuits and a computer-readable storage medium

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