Multi-core processor and control method thereof

Abstract

The invention provides a multi-core processor and a control method thereof. The multi-core processor is simple in structure and reasonable in design, does not conflict when accessing a memory, does not need commission or decision, and can keep high speed and high performance mutually. The multi-core processor comprises a group of processor cores A and B which are arranged in pairs, the shared memory is used for respectively connecting the processor cores A and the processor cores B which are arranged in pairs; a clock generation circuit configured to generate a clock signal; the clock signal is input into the processor core A and serves as a working time sequence of the processor core A to control interaction with the shared memory; the inverter is connected with the output end of the clock generation circuit and is configured to invert the clock signal to generate an inverted clock signal; and the inverted clock signal is input into the processor core B and serves as a working time sequence of the processor core B to control interaction with the shared memory.

Description

technical field [0001] The invention relates to a multi-core processor architecture, in particular to a multi-core processor and a control method thereof. Background technique [0002] A large number of multi-core processor architectures are used in current electronic systems; such as 4G / 5G cellular communication equipment, where each processing unit (ie: each processor core) is used to control certain hardware acceleration modules in real time, such as 4G / 5G communication A dedicated hardware module for channel codec acceleration in the device. The processing units (computer cores) used in these electronic systems are usually faced with high performance requirements. First, a high-speed main frequency is usually required. Second, it must be stronger than logical derivation, so performance delays caused by deep pipelines need to be avoided. Finally, and usually the most critical and challenging thing, the interrupt requests from the controlled hardware acceleration module...

AI Technical Summary

Problems solved by technology

However, if the depth of the processor pipeline increases, the response to the interrupt will slow down (because of the need to clean up the deeper and more complex processor pipeline), and at the same time affect the logical processing capability during normal work (deeper pipeline leads to longer data inter-dependent latency) - these are contrary to the need to improve system performance

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