Three-dimensional memory structure and manufacturing method thereof

Abstract

The invention provides a three-dimensional memory structure and a manufacturing method thereof. The manufacturing method comprises the following steps: providing a substrate and a stacking structure located on the substrate; forming a dummy channel hole penetrating through the stack structure in the stack structure, and filling an insulator in the dummy channel hole; and forming a grid line gap penetrating through the stacked structure in the stacked structure, and arranging the pseudo channel holes and the grid line gap adjacently, wherein the pseudo channel holes are arranged in the mode that the stacked structure between the pseudo channel holes and the grid line gap protrudes into the pseudo channel holes from the middle edges or / and the two side edges of the channel holes and the shape of the pseudo channel hole is set to increase the actual distance between the pseudo channel hole and the grid line gap. The problems that the subsequent process is affected and the electrical performance of the memory is abnormal due to serious shrinkage of the bottom size of the grid line gap can be avoided, meanwhile, the area of the memory does not need to be additionally occupied, and the integration level of the memory is ensured while the performance of the memory is improved.

Description

technical field [0001] The invention belongs to the field of semiconductor memory design and manufacture, in particular to a three-dimensional memory structure and a manufacturing method thereof. Background technique [0002] The improvement of the storage density of the memory device is closely related to the progress of the semiconductor manufacturing process. As the feature size of the semiconductor manufacturing process becomes smaller and smaller, the storage density of the memory device becomes higher and higher. In order to further increase storage density, memory devices with three-dimensional structures have been developed. A three-dimensional memory device includes a plurality of memory cells stacked along the vertical direction, which can double the integration level on a wafer per unit area and reduce the cost. [0003] In a three-dimensional memory device with a NAND structure, the array structure includes a gate stack structure, a channel column penetrating t...

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Problems solved by technology

The filling of the dummy channel hole is usually silicon dioxide, and the stacked structure is alternately formed of silicon dioxide and silicon nitride. The difference in effect or the stress difference between the dummy channel hole and the stack structure often leads to the shrinkage of the bottom size of the gate line gap adjacent to the dummy channel hole, which affects the progress of the subsequent process and causes abnormalities in the electrical properties of the memory.

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