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Interconnect circuit system, verification system and method

A circuit system and circuit module technology, applied in the field of interconnected circuit systems and verification systems, can solve the problems of high labor cost, inability to provide interconnection channels for multiple bus transmission protocols, poor reusability, etc., to achieve low labor cost and reusability. strong effect

Active Publication Date: 2021-07-13
北京燧原智能科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] At present, the existing interconnection bus model cannot provide a common interconnection channel for various bus transmission protocols, and the reusability is poor. The interconnection channel can only be redeveloped for different bus transmission protocols, and the labor cost is high.

Method used

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  • Interconnect circuit system, verification system and method
  • Interconnect circuit system, verification system and method
  • Interconnect circuit system, verification system and method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0038] figure 1 It is a schematic structural diagram of an interconnection circuit system provided by Embodiment 1 of the present invention. This embodiment is applicable to the case of verifying the collaborative work ability between core function modules under the condition that the interconnection circuit of the core circuit modules is not completed. Such as figure 1 As shown, the interconnection circuit system 10 provided by this embodiment includes: an interconnection bus model 11 and a protocol transaction pool 12, wherein,

[0039] The protocol transaction pool 12 is used to receive the protocol transaction sent by the circuit module 60 under test, store the protocol transaction, and generate a transaction to be transmitted corresponding to the protocol transaction, and send the transaction to be transmitted to the interconnection bus model 11 ; Wherein, the tested circuit module 60 includes a master circuit module 61 and a slave circuit module 62;

[0040] The interc...

Embodiment 2

[0091] Figure 7 A schematic structural diagram of a verification system for cooperating among integrated circuit modules provided in Embodiment 2 of the present invention. This embodiment is applicable to verifying the cooperating ability between core function modules under the condition that the interconnection circuit of the core circuit modules is not completed. Circumstances for verification. Such as Figure 7 As shown, the verification system for cooperating among integrated circuit modules specifically includes: a stimulus model 30, a function simulation model 20, a memory model 40, a scoreboard 50, and at least one interconnected circuit system 10 described in any embodiment of the present invention. . in,

[0092] The excitation model 30 is used to generate the command set of the tested circuit module 60, the configuration information of the interconnection circuit system and the configuration information of the memory model, and send the command set to the host ci...

Embodiment 3

[0140] Figure 9 Embodiment 3 of the present invention provides a flow chart of a method for verifying collaborative work between integrated circuit modules. This embodiment is applicable to verifying the collaborative work capability between core function modules under the condition that the interconnection circuit of the core circuit modules is not completed. The case of verification. The method can be executed by a verification system that cooperates among integrated circuit modules provided by an embodiment of the present invention. The system can be implemented in software and / or hardware, and can generally be integrated into a computer.

[0141] Such as image 3 As shown, the method for verifying the cooperative work between integrated circuit modules in this embodiment specifically includes:

[0142] S310. Generate the command set of the circuit module under test, the configuration information of the interconnection circuit system, and the memory model configuration i...

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Abstract

The embodiment of the invention discloses an interconnected circuit system, a verification system and a method. The interconnected circuit system includes: an interconnected bus model and a protocol transaction pool, the protocol transaction pool is used to receive the protocol transaction sent by the circuit module under test, store the protocol transaction, and generate a transaction to be transmitted corresponding to the protocol transaction , sending the transaction to be transmitted to the interconnection bus model; wherein, the circuit module under test includes a master circuit module and a slave circuit module, and the protocol transaction includes a protocol access transaction and a protocol feedback transaction; the interconnection The bus model is used to receive the transaction to be transferred, and realize the transfer of the transaction to be transferred between the master circuit module and the slave circuit module. The above-mentioned interconnection circuit system can provide a general interconnection channel for various bus transmission protocols, and has strong reusability.

Description

technical field [0001] Embodiments of the present invention relate to the technical field of integrated circuits, and in particular to an interconnected circuit system, a verification system and a method. Background technique [0002] In chip design, especially 5G and artificial intelligence chips, large-scale interconnection of core circuit modules is essential. In the early development of integrated circuits, more than 70% of the workload is in the verification stage. Among them, in the absence of interconnection circuits, completing the interconnection function verification of core circuit modules and providing feedback on performance and interconnection circuit design is an effective way to improve verification completeness, optimize function and performance design, and shorten verification time. In this situation without interconnected circuits, an interconnect bus model is essential. [0003] At present, the existing interconnection bus model cannot provide a common ...

Claims

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Application Information

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IPC IPC(8): G06F30/367
CPCG06F30/367
Inventor 杨兵
Owner 北京燧原智能科技有限公司
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