An Aided Chip Design Method for Reducing Simulation Time

Abstract

The invention discloses an auxiliary chip design method for reducing simulation time. First, a standard component library is established; then a reference model of an analog integrated circuit is established according to functional classification, including component library information for automatic calling and combination connection, parameter filling space and parts A blank module that needs to be manually designed; then select the reference model according to the required function in the development tool and fill in the parameters, generate the top-level circuit of the schematic diagram, each module sub-circuit and the form required for module verification, and import it into the schematic diagram editor to complete Schematic design; finally import the layout design tool, call the corresponding layout in the standard component library and draw the layout, verify and integrate the complete drawing. Applying the method of the present invention can reduce the time-consuming caused by re-layouting the layout due to the adjustment of the schematic diagram, and also reduce the simulation time required for most of the module function verification, and greatly accelerate the speed of chip design.

Description

technical field [0001] The invention relates to a semiconductor chip design method, in particular to an auxiliary chip design method for reducing simulation time in the design of an analog integrated circuit. Background technique [0002] like figure 1 As shown in the figure, in the current design of analog circuit chips, each functional module is drawn separately, and finally the wiring is placed uniformly to form a complete chip. The principle design part often creates a new circuit structure or modifies part of the parameters of the module due to the actual design requirements; The layout part needs to make the corresponding actual layout circuit according to the modification of the principle part. [0003] The parameters modified due to the schematic diagram part vary from person to person due to the personal experience of the principle designer. For example, in order to reduce the current of a branch in the circuit, the resistance of the branch can be increased, or th...

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Problems solved by technology

[0004] In order to overcome the deficiencies of the above-mentioned prior art, the object of the present invention is to propose an auxiliary chip design method that reduces simulation time, and solve the problems of difficult adjustment of schematic diagram and layout and long simulation time in chip design

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