A Modeling Method for Mosfet Gate-Source Voltage Disturbance Conduction Path Model

Abstract

The invention provides a modeling method of a MOSFET gate-source voltage interference conduction path model, which includes a double-loop transfer function describing the interference conduction process of pulse voltage and pulse current, and a characteristic equation of a standard second-order system describing the interference conduction path. This model is used to reveal the gate-source voltage interference mechanism that occurs when MOSFETs are turned on and off at high speed in high-frequency high-power converters. The interference conduction path model can comprehensively consider the impact of pulse voltage and pulse current on MOSFET gate-source voltage interference , used to intuitively and quickly judge the rationality of MOSFET driving parameters, MOSFET package structure, and PCB layout design in the power conversion system.

Description

technical field [0001] The invention relates to a modeling method for a MOSFET gate-source voltage interference conduction path model. Background technique [0002] In general, the working voltage of SiC MOSFET (about kV level) is much higher than the working current (about A level) in value. Therefore, the pulse voltage is the main interference source of gate-source voltage interference, although in terms of value, considering the pulse voltage The mathematical analysis of interference has good accuracy within the allowable range of error, but under the premise of studying the package difference and the interference caused by the driving resistance to the gate-source voltage, the interference of the pulse current cannot be ignored. The interference of the pulse current on the gate-source voltage can be roughly divided into two categories: the first type, the distributed voltage interference is induced in the drive circuit through the change of the space electromagnetic fiel...

AI Technical Summary

Problems solved by technology

However, for the second type of conducted interference, there is still a lack of systematic theoretical guidance and engineering design solutions in the field of power electronics

[0003] In the second type of conducted interference, drastic changes in the drain-source voltage and current are conducted through the Miller capacitance, causing spikes and oscillations in the gate-source voltage, affecting the stability of the gate-source voltage, which will increase the loss of the converter, and even cause the bridge arm to pass through, The breakdown of gate electrolyte seriously threatens the performance improvement and safe and reliable application of MOSFET

However, these complex mechanism models only consider the voltage spikes caused by disturbances, and lack explanations for disturbance oscillations; moreover, in the modeling process, too many non-dominant stray parameters are introduced

Therefore, using these complex mechanism models, it is still difficult to directly face engineering applications and give design guidelines considering gate pressure stress; the method of reducing SiC MOSFET gate pressure stress has not yet been fully integrated into the design of high-power converter systems

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