MOSFET gate-source voltage interference conduction path model

Abstract

The invention provides an MOSFET gate-source voltage interference conduction path model. The MOSFET gate-source voltage interference conduction path model comprises a double-loop transfer function fordescribing a pulse voltage and pulse current interference conduction process and a characteristic equation for describing a standard second-order system of an interference conduction path. The modelis used for revealing a gate-source voltage interference mechanism occurring when a high-frequency high-power converter and an MOSFET are turned on and turned off at a high speed, and the interferenceconduction path model can comprehensively consider the influence of pulse voltage and pulse current on MOSFET gate-source voltage interference and is used for visually and rapidly judging the rationality of the MOSFET driving parameters, an MOSFET packaging structure and the PCB layout designin in a power conversion system .

Description

technical field [0001] The invention relates to a MOSFET gate-source voltage interference conduction path model. Background technique [0002] In general, the working voltage of SiC MOSFET (about kV level) is much higher than the working current (about A level) in value. Therefore, the pulse voltage is the main interference source of gate-source voltage interference, although in terms of value, considering the pulse voltage The mathematical analysis of interference has good accuracy within the allowable range of error, but under the premise of studying the package difference and the interference caused by the driving resistance to the gate-source voltage, the interference of the pulse current cannot be ignored. The interference of the pulse current on the gate-source voltage can be roughly divided into two categories: the first type, the distributed voltage interference is induced in the drive circuit through the change of the space electromagnetic field, which belongs to th...

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Problems solved by technology

However, for the second type of conducted interference, there is still a lack of systematic theoretical guidance and engineering design solutions in the field of power electronics

[0003] In the second type of conducted interference, drastic changes in the drain-source voltage and current are conducted through the Miller capacitance, causing spikes and oscillations in the gate-source voltage, affecting the stability of the gate-source voltage, which will increase the loss of the converter, and even cause the bridge arm to pass through, The breakdown of gate electrolyte seriously threatens the performance improvement and safe and reliable application of MOSFET

However, these complex mechanism models only consider the voltage spikes caused by disturbances, and lack explanations for disturbance oscillations; moreover, in the modeling process, too many non-dominant stray parameters are introduced

Therefore, using these complex mechanism models, it is still difficult to directly face engineering applications and give design guidelines considering gate pressure stress; the method of reducing SiC MOSFET gate pressure stress has not yet been fully integrated into the design of high-power converter systems

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