Semiconductor structure preparation method and semiconductor device

Abstract

The invention discloses a semiconductor structure preparation method comprising the following steps that: step 1, a first substrate layer and a second substrate layer are formed, wherein the first substrate layer is composed of a first thin film layer and a second thin film layer which are alternately deposited, and the second substrate layer is composed of a first thin film layer and a third thinfilm layer which are alternately deposited on the first substrate layer; the first thin film layer is a silicon oxide or silicon nitride thin film, the second thin film layer is an intrinsic or P-type amorphous layer, the third thin film layer is an N-type amorphous layer, a first groove is etched in the second thin film layer, and a second groove is etched in the third thin film layer.

Description

technical field [0001] The invention relates to a method for preparing a semiconductor structure and a semiconductor device, in particular to a method for simultaneously integrating P-type and N-type stacked nanowires in a three-dimensional direction and a semiconductor device prepared by the method, belonging to the field of microelectronic technology. Background technique [0002] With the continuous miniaturization of devices, the structure of transistors has also changed from a traditional planar structure to a three-dimensional direction. After the 3nm process node, the large distance between P-type transistors and N-type transistors will become the main reason for hindering the further scaling of devices. Using the current partition doping process, the distance between PMOS and NMOS is about 300 nm. If the P-type Transistors and N-type transistors are stacked vertically to form three-dimensional complementary devices, which can break through this bottleneck. However, ...

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Problems solved by technology

However, at present, three-dimensional complementary devices are mainly prepared by N-type transistors on top of P-type transistors. This process not only requires extremely high temperature for subsequent processes, but also is relatively complicated.

This problem can be solved if nanowires with different doping types can be integrated simultaneously in three dimensions, but no such technology has been disclosed so far.

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