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Instruction coupling device, method and equipment for processor core verification and storage medium

A technology of processor core and coupling device, applied in program control device, electrical digital data processing, special data processing application, etc., can solve problems such as low test coverage convergence

Active Publication Date: 2020-11-13
PENG CHENG LAB
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The main purpose of the present invention is to provide an instruction coupling device, method, equipment and storage medium for processor core verification, aiming to solve the technical problem of low convergence of test coverage in the current processor core verification instruction coupling method

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  • Instruction coupling device, method and equipment for processor core verification and storage medium
  • Instruction coupling device, method and equipment for processor core verification and storage medium
  • Instruction coupling device, method and equipment for processor core verification and storage medium

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Embodiment Construction

[0036] It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0037] The present invention provides an instruction coupling device for processor core verification, referring to figure 1 , figure 1 A schematic diagram of a preferred structure of the instruction coupling device for processor core verification of the present invention.

[0038] The instruction coupling device verified by the processor core is applied to a RISC-V processor, and the instruction coupling device verified by the processor core includes: a configuration information parser 10, a constraint solver 20, an instruction generator 30 and an instruction transmitter 40 , wherein, the configuration information parser 10 is used to resolve the configuration information corresponding to the test case in the RISC-V processor core into the corresponding first constraint data; the constraint solver 20 is used to analy...

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PUM

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Abstract

The invention discloses an instruction coupling device, method and equipment for processor core verification and a storage medium. The instruction coupling device for processor core verification comprises a configuration information analyzer, a constraint solver, an instruction generator and an instruction emitter, wherein the configuration information analyzer is used for analyzing configurationinformation of a test case in a processor core into first constraint data; the constraint solver is used for performing constraint solving based on the first constraint data, determining a constraintsolving result and generating second constraint data based on the first constraint data; the instruction generator is used for generating a coupling instruction or a non-coupling instruction based onthe second constraint data; and the instruction emitter is used for sending the coupling instruction or the non-coupling instruction to a driver and feeding back the generated instruction informationto the constraint solver. According to the invention, the configuration information is coupled to the instruction information in the instruction emitter, so that the instructions are associated and dependent with each other, and the convergence efficiency of the test coverage rate is improved.

Description

technical field [0001] The invention relates to the field of instruction coupling and logic testing, in particular to an instruction coupling device, method, equipment and storage medium for processor core verification. Background technique [0002] At present, the processor core verification command coupling method is mainly to generate configuration information from test cases and send the configuration information to the configuration information parser. The configuration information parser parses the received configuration information into constraints, and the constraints are processed by the constraint solver. The instruction generator can generate instructions within the set specified by the constraints. The generated commands are sent by the command transmitter to the driver for processing. The constraint solver, instruction generator, and instruction emitter run for multiple rounds, generating one instruction per round, until the total number of issued instructions ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/445G06F30/327G06F11/36
CPCG06F9/4451G06F11/3676G06F11/3684G06F30/327
Inventor 张延飞张凡李睿高峰
Owner PENG CHENG LAB
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