3D memory device and manufacturing method thereof

Abstract

The invention discloses a 3D memory device and a manufacturing method thereof. The manufacturing method of the 3D memory device comprises the following steps: forming a stepped insulating laminated structure on a semiconductor substrate, wherein each step comprises a sacrificial layer and an interlayer insulating layer positioned below the sacrificial layer; forming a protective layer on at leastpart of the exposed surface of the sacrificial layer; forming a dielectric layer covering the insulating laminated structure above the protective layer; replacing the sacrificial layer with a gate conductor layer to form a gate laminated structure; and forming a conductive channel communicated with the gate conductor layer on at least one step, wherein the protective layer serves as a stop layer for forming the conductive channel, and the conductive channel is at least partially contacted with the gate conductor layer. According to the manufacturing method, the protective layer is formed on the surface of the laminated structure through treatment, and the protective layer is used as a stop layer to execute an etching process to form step region contact, so that the etching difficulty is reduced under the condition that the thickness of the single-layer dielectric laminated layer is reduced, and the reliability of the memory device is improved.

Description

technical field [0001] The present invention relates to memory technology, and more particularly, to 3D memory devices and manufacturing methods thereof. Background technique [0002] The improvement of the storage density of the memory device is closely related to the progress of the semiconductor manufacturing process. As the feature size of the semiconductor manufacturing process becomes smaller and smaller, the storage density of the memory device becomes higher and higher. In order to further increase storage density, memory devices with a three-dimensional structure (ie, 3D memory devices) have been developed. A 3D memory device includes a plurality of memory cells stacked in a vertical direction, which can double the integration level on a wafer per unit area and reduce the cost. [0003] In the 3D NAND structure, it mainly includes a gate stack structure, a channel column penetrating the gate stack structure, and a conductive channel. The gate stack structure is us...

AI Technical Summary

Problems solved by technology

As the number of stacked layers in the 3D NAND structure continues to increase, the total film thickness of the dielectric layer continues to increase, which will lead to an increase in the difficulty of etching deep holes / deep grooves

Generally, the difficulty of etching deep holes / grooves is reduced by appropriately reducing the thickness of the single-layer dielectric stack, but the etching stop layer corresponding to the step area used to form the contact hole of the conductive channel will also be correspondingly thinned and increased. Reduce the difficulty of etching and reduce the process window

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