Processor transient attack defense method based on cache random invalidation

Abstract

The embodiment of the invention provides a cache management method. The method comprises the following steps: in response to a memory access request, loading a data block containing data required by aspeculated memory access loading instruction into a common cache, and executing the following operations when the cached data block of the common cache is kicked out of the common cache by the data block loaded by the speculated memory access loading instruction: loading the kicked-out data block into a shadow cache of the same-level cache; and randomly selecting an interference cache line from all cache lines of a common cache, writing a data block of the interference cache line into a next-level storage medium, and then invalidating the interference cache line. According to the invention, an attacker can be prevented from kicking a specific data block out of a certain level of cache by using a speculated memory access loading instruction, so that the access speed of the attacker is prevented from being changed; in addition, the interference cache line is randomly selected, and the data block of the interference cache line is set to be invalid, so that the access speed of the data block of the interference cache line is changed to interfere an attacker, and a secret value can be effectively prevented from being detected by a side channel attack.

Description

technical field [0001] The present invention relates to the field of computer technology, in particular to a mechanism and technology for improving processor security, and more specifically to a method for defending against transient attacks of a processor based on random cache invalidation. Background technique [0002] For optimal processor performance, the memory must be able to keep up with the speed of the processor. That is, when the processor is executing instructions, we don't expect it to stall execution while waiting for instructions or operands. Therefore, a cache (Cache) is introduced between the registers and main memory of modern processors. In this way, a computer's memory is organized into a hierarchy. The topmost layer (the layer closest to the processor) is the register in the processor, followed by one or more levels of cache, when using multi-level cache, usually the first, second, third level cache, etc. Labeled L1, L2, L3, etc., and below that is mai...

AI Technical Summary

Problems solved by technology

The main problem of this type of attack is that the attacker uses out-of-bounds speculative execution to change the cache layout, and then obtains the secret through side channel detection.

Therefore, it is necessary to improve the existing technology, so that it is difficult for attackers to accurately detect the change of cache layout caused by speculative execution out of bounds, so as to improve the security of the processor

Images