Method and device for confirming physical location of failure address in chip storage area

Abstract

A method and device for confirming the physical location of a failure address in a chip storage area. The method performs electrical verification on the storage chip, obtains the failure row address and the failure column address corresponding to the abnormal channel storage unit, and then finds the failure row The abnormal word line corresponding to the address is used to mark the position of the abnormal word line; the abnormal word line is electrically connected to several adjacent word lines on both sides of the abnormal word line to form a word line connection area; the memory chip is Place it in an electron microscope for scanning, and identify the word line connection area through the difference in image contrast between light and dark; move the memory chip along the word line connection area with different contrast in the electron microscope to find the abnormal bit line corresponding to the failed column address and performing physical position marking on the abnormal channel memory cell corresponding to the intersection of the abnormal word line and the abnormal bit line. The method of the invention improves the accuracy of the physical position marking.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method and device for confirming the physical location of a failure address in a chip storage area. Background technique [0002] NAND flash memory is a better storage device than hard disk drives, and it has been widely used in electronic products as people pursue non-volatile storage products with low power consumption, light weight and high performance. At present, the NAND flash memory with a planar structure is close to the limit of practical expansion. In order to further increase the storage capacity and reduce the storage cost per bit, a 3D NAND memory with a 3D structure is proposed. [0003] The manufacturing process of the existing 3D NAND memory includes: providing a substrate on which a stacked structure in which isolation layers and sacrificial layers are alternately stacked; etching the stacked structure to form an exposed substrate surface in the stack...

AI Technical Summary

Problems solved by technology

[0005] However, the accuracy of the physical location of the failed storage unit found by the existing method is limited, which may easily cause bad analysis failure

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