Method and device for confirming physical position of failure address in chip storage area

Abstract

The invention discloses a method and a device for confirming the physical position of a failure address in a chip storage area, and the method comprises the steps: carrying out the electrical verification of a storage chip, obtaining a failure row address and a failure column address corresponding to an abnormal channel storage unit, finding an abnormal word line corresponding to the failure row address, and carrying out the position marking of the abnormal word line; electrically connecting the abnormal word line with a plurality of adjacent word lines on two sides of the abnormal word line to form a word line connection area; placing the memory chip in an electron microscope for scanning, and identifying a word line connection area according to different image light and shade contrast ratios; and moving a memory chip along the word line connection areas with different contrasts in an electron microscope, finding an abnormal bit line corresponding to the failure column address, and performing physical position marking on an abnormal channel memory unit corresponding to the intersection of the abnormal word line and the abnormal bit line. According to the method, the accuracy of physical position marking is improved.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method and device for confirming the physical location of a failure address in a chip storage area. Background technique [0002] NAND flash memory is a better storage device than hard disk drives, and it has been widely used in electronic products as people pursue non-volatile storage products with low power consumption, light weight and high performance. At present, the NAND flash memory with a planar structure is close to the limit of practical expansion. In order to further increase the storage capacity and reduce the storage cost per bit, a 3D NAND memory with a 3D structure is proposed. [0003] The manufacturing process of the existing 3D NAND memory includes: providing a substrate on which a stacked structure in which isolation layers and sacrificial layers are alternately stacked; etching the stacked structure to form an exposed substrate surface in the stack...

AI Technical Summary

Problems solved by technology

[0005] However, the accuracy of the physical location of the failed storage unit found by the existing method is limited, which may easily cause bad analysis failure

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