Implementation method of global constraint-based lock instruction pseudo-random self-comparison verification model

A global constraint and verification model technology, applied in random number generators, instruments, electrical digital data processing, etc., can solve the problems of poor randomness of test incentives, single test scenarios, poor inheritance, etc., and achieve comprehensive stimulus testing and accurate calibration , strong pseudo-random effect

Active Publication Date: 2020-01-14
上海高性能集成电路设计中心
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Problems solved by technology

[0007] The present invention provides a method for realizing a lock instruction pseudo-random self-comparison verification model based on global constraints, which solves the problems of poor randomness of test incentives, Problems such as cumbersome code, poor inheritance, difficult maintenance, and single test scenarios, etc., and at the same time, the verification of the correctness of the test results is realized, which increases the compatibility of the environment

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  • Implementation method of global constraint-based lock instruction pseudo-random self-comparison verification model
  • Implementation method of global constraint-based lock instruction pseudo-random self-comparison verification model
  • Implementation method of global constraint-based lock instruction pseudo-random self-comparison verification model

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Embodiment Construction

[0030] Below in conjunction with specific embodiment, further illustrate the present invention. It should be understood that these examples are only used to illustrate the present invention and are not intended to limit the scope of the present invention. In addition, it should be understood that after reading the teachings of the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms also fall within the scope defined by the appended claims of the present application.

[0031] Embodiments of the present invention relate to an implementation method of a lock instruction pseudo-random self-comparison verification model based on global constraints, such as figure 1 shown, including the following steps:

[0032] 1. In order to solve the poor randomness of test incentives, a lock sharing structure that can be seen by test scenarios and test sequence libraries is established in the pseudo-random st...

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Abstract

The invention relates to an implementation method of a global constraint-based lock instruction pseudo-random self-comparison verification model. The implementation method comprises the following steps: establishing a lock sharing structure which can be seen by a tested scene and a test sequence library; generating a lock sharing structure table according to the global constraint, wherein the locksharing structure table at least comprises two lock sharing structures; randomly selecting a lock sharing structure to be executed by the core; after the lock is successfully locked, updating the critical zone address content and the global critical zone variable of the lock sharing structure; releasing the lock sharing structure; and after all the cores finish the lock execution operation, randomly appointing one core to perform traversal check on all the lock sharing structures in the lock sharing structure table. According to the invention, the problems of poor test excitation randomness,tedious codes, poor inheritance, difficult maintenance, single test scene and the like in the existing test method are solved, the correctness of the test result is verified, and the environmental compatibility is improved.

Description

technical field [0001] The invention relates to the technical field of microprocessor verification, in particular to a method for realizing a lock instruction pseudo-random self-comparison verification model based on global constraints. Background technique [0002] In the high-performance processor instruction set, the lock operation instruction can quickly realize the setting and clearing operation of the shared resource, ensuring that the shared resource can be processed serially. At the software level, the verification of this type of instruction is mainly carried out by the system running a special self-checking program. At the hardware level, the simulation verification of this type of instruction mainly adopts the method of manually writing assembly stimuli, that is, writing different assembly stimuli for different test points for testing, and at the same time verifying that the results "follow the design", that is, collecting design signals to confirm whether the loc...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/58
CPCG06F7/582
Inventor 胡向东蒋祥鹏巨鹏锦罗先伟徐小沛
Owner 上海高性能集成电路设计中心
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