Low-power-consumption ultra-high-speed high-precision analog-to-digital converter

An analog-to-digital converter, ultra-high-speed technology, applied in the direction of analog-to-digital converter, analog/digital conversion, analog/digital conversion calibration/test, etc., to achieve the effect of avoiding power consumption, eliminating influence, and shortening output time

Active Publication Date: 2019-10-01
成都铭科思微电子技术有限责任公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] To sum up, in response to the demand for low-power ultra-high-speed high-precision ADCs in the market, there is currently no standard architecture design. According to different index requirements, the ADC architecture requires targeted design.

Method used

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Embodiment 1

[0039] The present invention designs a low-power ultra-high-speed high-precision analog-to-digital converter, which is a low-power ADC circuit architecture with a 10-bit resolution gigahertz sampling frequency built in an IC chip, such as figure 1 , figure 2As shown, the following configuration structure is adopted in particular: including input circuit, low-speed ADC, 1 / 16 frequency divider and output circuit, the input circuit is connected to the low-speed ADC, the low-speed ADC is connected to the output circuit, and the 1 / 16 frequency divider is respectively It is connected with the input circuit and the low-speed ADC; the input circuit samples the input signal at a frequency of 1.6GHz; the low-speed ADC acquires the signal from the input circuit at a frequency of 100MHz.

[0040] As a preferred setting scheme, the low-power ultra-high-speed high-precision analog-to-digital converter is mainly composed of four major parts: an input circuit, a low-speed ADC, a 1 / 16 frequen...

Embodiment 2

[0042] This embodiment is further optimized on the basis of the foregoing embodiments, and the same parts as the technical solutions of the preceding embodiments will not be repeated here, such as figure 1 , figure 2 As shown, further in order to better realize the present invention, the following setting method is adopted in particular: the low-speed ADC includes 16 SAR_ADCs that work in time-division and alternate sampling, the SAR_ADCs are all connected in parallel with the input circuit, and the 1 / 16 frequency divider is controlled and connected SAR_ADC, SAR_ADC is connected with the output circuit.

[0043] As a preferred setting scheme, the low-speed ADC is mainly composed of 16 SAR_ADCs that work in time-division alternate sampling. The 16 SAR_ADCs that work in time-division alternate The SAR_ADC with alternate sampling work is connected, and the 1 / 16 frequency divider controls the connection of 16 SAR_ADC with time-division alternate sampling work, and the 16 SAR_ADC...

Embodiment 3

[0045] This embodiment is further optimized on the basis of any of the above-mentioned embodiments, and the same parts as the technical solutions of the foregoing embodiments will not be repeated here, such as figure 1 , figure 2 As shown, further in order to better realize the present invention, the following setting method is adopted in particular: a local capacitance is arranged at any reference voltage access point of SAR_ADC, as a preferred setting scheme, at the reference voltage connection point of each SAR_ADC The input point introduces a local capacitor (C_DEC) to reduce the dynamic mismatch between reference voltages, thereby greatly reducing the gain mismatch between SAR_ADC and improving the performance of ultra-high-speed and high-precision analog-to-digital converters.

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PUM

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Abstract

The invention discloses a low-power-consumption ultra-high-speed high-precision analog-to-digital converter. The analog-to-digital converter comprises an input circuit, a low-speed ADC, a 1 / 16 frequency divider and an output circuit, the input circuit is connected with the low-speed ADC, the low-speed ADC is connected with the output circuit, and the 1 / 16 frequency divider is connected with the input circuit and the low-speed ADC; the input circuit samples an input signal by adopting the frequency of 1.6 GHz. The low-speed ADC is used for acquiring signals from the input circuit at the frequency of 100MHz; the low-power-consumption ADC circuit architecture with the 10-bit resolution gigahertz sampling frequency is constructed in an IC chip.

Description

technical field [0001] The invention relates to the technical field of analog-to-digital conversion, in particular to an ultra-high-speed and high-precision analog-to-digital converter with low power consumption. Background technique [0002] With the continuous increase in the bandwidth requirements of input analog signals and the increase in the demand for direct sampling of radio frequency signals, there is a huge market demand for ultra-high-speed analog-to-digital converter (ADC) chips. [0003] The existing ultra-high-speed ADC architectures mainly include Flash, folding interpolation, Pipeline, and time interleaving. [0004] Flash ADC, also known as parallel ADC, is the simplest ADC architecture in the industry that can achieve the highest conversion rate. However, as the resolution increases, the number of comparators required increases exponentially, resulting in chip Significant increase in area and power consumption. In addition, the offset mismatch between the...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/10H03M1/00H03M1/12
CPCH03M1/002H03M1/1009H03M1/121
Inventor 徐振涛王现喜刘学杨荣彬胡国林
Owner 成都铭科思微电子技术有限责任公司
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