Laminated structure for three-dimensional memory, three-dimensional memory and preparation method thereof

Abstract

The invention provides a stacked structure for a three-dimensional memory, a three-dimensional memory and a preparation method thereof, including sacrificial layers and inter-gate dielectric layers alternately stacked up and down; The channel via hole of the layer structure, along the thickness direction of the laminated structure, the width of each part of the channel via hole is not the same; the thickness of the sacrificial layer is proportional to the width of the channel via hole and the thickness of the inter-gate dielectric layer is proportional Inversely proportional to the width of the via hole. The stacked structure for the three-dimensional memory of the present invention can compensate for the influence of the inconsistency of the width of the channel via hole formed in the stacked structure and the poor shape of the channel via hole; the stacked layer of the three-dimensional memory based on the present invention In the three-dimensional memory formed by the structure, all memory cells have the same programming / erasing speed, the coupling effect of the erased state is better, the performance of all memory cells has better uniformity, the threshold voltage of the three-dimensional memory is narrow, and the performance of the three-dimensional memory Good stability.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit design and manufacture, and in particular relates to a stacked structure for a three-dimensional memory, a three-dimensional memory and a preparation method thereof. Background technique [0002] In the existing semiconductor process, with the continuous improvement of memory density requirements, the number of stacked structures in the three-dimensional memory is continuously increased, and the aspect ratio of the channel vias (CH) formed in the stacked structures is also increasing. Higher and higher. For channel vias with a high aspect ratio, due to the limitation of the existing etching process, the bottom morphology of the formed channel vias is relatively poor, for example, the morphology of the bottom of the channel vias will be deformed (distortion) Or there are defects such as streaks (striation), and at the same time, the width of the channel vias formed is inconsistent, for ...

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Problems solved by technology

[0003] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a stacked structure for a three-dimensional memory, a three-dimensional memory and its preparation method. The layer structure, three-dimensional memory and its preparation method are used to solve the problem in the prior art that the memory cells corresponding to the smaller part of the channel via hole width are compared with the memory cells corresponding to the larger part of the channel via hole width. The programming / erasing speed is fast, the memory cells corresponding to the smaller part of the channel via hole have more serious read interference, the erased state coupling effect is poor, and the characteristics of the memory cells in each part of the memory are inconsistent, resulting in the threshold voltage of the three-dimensional memory The distribution is wide, which affects the performance of the three-dimensional memory and other issues

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