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Memory testing device and method

A technology of memory testing and memory, which is applied in the direction of faulty hardware testing methods, error detection/correction, and detection of faulty computer hardware. Test production delays and other issues to achieve the effects of improving test efficiency, reliable design principles, and cost savings

Inactive Publication Date: 2019-09-06
SUZHOU LANGCHAO INTELLIGENT TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] Due to the fact that most of the current memory tests are still in the low-efficiency state of a single memory or 2-4 memories in a single machine, it cannot meet the needs of mass production for rapid inspection of qualified memory, which leads to delays in memory testing for production
[0004] Based on the problem that the existing memory test cannot be tested in large quantities, a modular memory test module architecture is proposed to solve the existing problems

Method used

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  • Memory testing device and method
  • Memory testing device and method

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Experimental program
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Embodiment 1

[0025] like figure 1 As shown, this embodiment provides a memory testing device, including a test control module 1 , a test execution module 2 and a power supply, and the power supply supplies power to the test control module 1 and the test execution module 2 . The test control module includes a control chip C2 and a first communication chip C1, and the control chip C2 is communicatively connected with the first communication chip C1. The test control module is also provided with a serial port 4, and the serial port is electrically connected to the control chip C2 as an I / O device of the control chip C2. The test execution module includes a second communication chip C1 and six memory test servers, each memory test server is communicatively connected to the second communication chip C1, and each memory test server can mount 4 memory sticks. The first communication chip C1 is electrically connected to the second communication chip C1 to realize communication between the test co...

Embodiment 2

[0027] This embodiment provides a memory testing device, including a test control module 1 and a test execution module 2, each of which has its own power supply. The test control module includes a control chip C2 and a first communication chip C1, and the control chip C2 is communicatively connected with the first communication chip C1. The test control module is also provided with a serial port 4, and the serial port is electrically connected to the control chip C2 as an I / O device of the control chip C2. The test execution module includes a second communication chip C1 and six memory test servers, each memory test server is communicatively connected to the second communication chip C1, and each memory test server can mount three memory sticks. The first communication chip C1 and the second communication chip C1 are electrically connected through a synchronous serial bus to realize communication between the test control module 1 and the test execution module 2 .

Embodiment 3

[0029] Please refer to figure 2 , this embodiment provides a memory testing method, which uses two memory test servers A and B, and each memory test server mounts three memory sticks 1, 2, and 3 as an example for illustration, including the following steps:

[0030] S1. Burn the memory test program into the control chip.

[0031] Connect the personal computer and the serial port of the test control module through the data cable. After connecting the personal computer to the serial port, control the control chip C2 of the test control module through the personal computer to start the simulated DOS or UEFI-like operating environment, and import the memory test program through the serial port connection. to the control chip C2.

[0032] S2, through I 2 The C bus sends the memory test program in the control chip to each test execution group.

[0033] The control chip C2 sends the memory test program to the first communication chip C1, and the first communication chip C1 passes...

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Abstract

The invention provides a memory test device and a test method. The memory test device comprises a test control module and a test execution module, the test control module comprises a control chip anda first communication chip, and the control chip is in communication connection with the first communication chip; the test execution module comprises a second communication chip and a plurality of test execution groups, and the plurality of test execution groups are in communication connection with the second communication chip; the test execution group comprises a terminal capable of mounting atested memory; and the first communication chip is electrically connected with the second communication chip. Batch automatic testing can be carried out on the memory banks, the testing efficiency isgreatly improved, a C2 control chip is adopted in the testing control module, the structure is simple, a special control server is not needed, and the cost is saved.

Description

technical field [0001] The invention belongs to the technical field of storage device testing, and in particular relates to a memory testing device and a testing method. Background technique [0002] With the advancement of digital technology, whether it is a personal computer or a server, memory, a key component of high data exchange, is constantly being upgraded and replaced. It is precisely because memory plays a key role in data exchange performance that people are increasingly controlling memory quality. [0003] Due to the fact that most of the current memory tests are still in the low-efficiency state of a single or 2-4 memory in a single machine, it cannot meet the needs of mass production for rapid inspection of qualified memory, which leads to delays in memory testing for production. [0004] Based on the problem that the existing memory test cannot be tested in large quantities, a modular memory test module architecture is proposed to solve the existing problems....

Claims

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Application Information

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IPC IPC(8): G06F11/22
CPCG06F11/2205G06F11/2273
Inventor 邢科钰
Owner SUZHOU LANGCHAO INTELLIGENT TECH CO LTD
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