Integrated chip and test method thereof

Abstract

The invention provides an integrated chip and a test method thereof, and relates to the technical field of integrated circuits. The integrated circuit comprises a low speed universal interface, an eFPGA (e-Field-Programmable Gate Array) circuit and at least one functional circuit; the low speed universal interface is connected with the eFPGA circuit, and the eFPGA circuit is connected with each functional circuit; the low speed universal interface is used for receiving a test file transmitted by an external intelligent terminal, and transmitting the test file to the eFPGA circuit; the eFPGA circuit is used for acquiring a test signal of a target functional circuit based on the received test file, and feeding the acquired test signal back to the low speed universal interface; and the low speed universal interface is further used for transmitting the received test signal to the intelligent terminal, so that the intelligent terminal obtains a functional test result of the target functional circuit. The integrated chip provided by the invention can effectively reduce the number of IO interfaces required by the functional test, and can also effectively alleviate the limitation of the chip signal rate on the functional test.

Description

technical field [0001] The invention relates to the technical field of integrated chips, in particular to an integrated chip and a testing method thereof. Background technique [0002] With the increasing demand for processing power of electronic equipment, chips are one of the main factors determining the processing power of electronic equipment, and their internal design is becoming increasingly complex. In order to ensure that the complex functions inside the chip can be fully verified and tested, most chips will be internally Increase design for testability. At present, the function of the chip is mainly tested through the IO (Input / Output, input / output) interface of the chip. Therefore, the available number of IOs determines the testable performance of the chip. In addition, because the existing chip cannot pass through the high-speed signal Functional test, so the functional test of the chip is limited by the number of IO interfaces of the chip and the signal rate of ...

AI Technical Summary

Problems solved by technology

At present, the function of the chip is mainly tested through the IO (Input / Output, input / output) interface of the chip. Therefore, the available number of IOs determines the testable performance of the chip. In addition, because the existing chip cannot pass through the high-speed signal Functional test, so the functional test of the chip is limited by the number of chip IO interfaces and the signal rate of the chip

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