A three-terminal compact composite SCR device for full-chip ESD protection

Abstract

The invention belongs to the field of electronic technology, and specifically relates to the design of an electrostatic discharge (ESD) protection circuit, and specifically provides a three-terminal compact composite SCR device (CCSCR) for full-chip ESD protection, including a main discharge CCSCR device and an RC auxiliary Trigger detection circuit; the main discharge CCSCR device is a three-terminal device, which introduces three parasitic SCR paths on the basis of the CMOS device structure, so as to achieve highly robust full-chip ESD protection in a smaller layout area; RC auxiliary trigger detection The introduction of the circuit can further reduce the trigger voltage of the device; in addition, the CCSCR device of the present invention can also be used as a two-terminal device to provide ESD protection between any IO port and the power supply.

Description

technical field [0001] The invention belongs to the field of electronic technology, and in particular relates to the design of an electrostatic discharge (Electro-Static discharge, ESD for short) protection circuit, especially a silicon controlled rectifier SCR (Silicon Controlled Rectifier for short SCR) used for full-chip ESD protection. Background technique [0002] In the process of semiconductor chip manufacturing, packaging and transportation, and user use, ESD phenomena are ubiquitous; the instantaneous high-voltage electrostatic pulse generated by ESD can flow into the chip through the pins of the chip, causing gate oxide breakdown and damage to the internal circuit of the chip. unable to work properly. In recent years, with the rapid development of the electronics industry, the line width of integrated circuits has been further reduced, the integration level of chips has been further increased, and the gate oxide layer of MOSFET devices has become thinner and thinne...

AI Technical Summary

Problems solved by technology

[0005] In the full-chip ESD protection circuit, a single device is required between IO and VDD and VSS as an ESD protection device, which occupies a large chip area. In addition, in order to quickly discharge the ESD current under ESD stress conditions, it is necessary to An effective ESD clamp circuit is repeatedly inserted between the VDD and VSS supply lines at a suitable distance to provide a low impedance path between the VDD and VSS supply lines, which also consumes a lot of chip area

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