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A three-terminal compact composite SCR device for full-chip ESD protection

A composite, full-chip technology, applied in the field of electronics, can solve problems such as occupation, large chip area, and chip area loss, and achieve the effects of small area, reduced trigger voltage, and reduced ESD current

Active Publication Date: 2022-01-25
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] In the full-chip ESD protection circuit, a single device is required between IO and VDD and VSS as an ESD protection device, which occupies a large chip area. In addition, in order to quickly discharge the ESD current under ESD stress conditions, it is necessary to An effective ESD clamp circuit is repeatedly inserted between the VDD and VSS supply lines at a suitable distance to provide a low impedance path between the VDD and VSS supply lines, which also consumes a lot of chip area

Method used

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  • A three-terminal compact composite SCR device for full-chip ESD protection
  • A three-terminal compact composite SCR device for full-chip ESD protection
  • A three-terminal compact composite SCR device for full-chip ESD protection

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Embodiment Construction

[0023] The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0024] This embodiment provides a three-terminal compact composite SCR device for full-chip ESD protection, such as Figure 2 to Figure 7 shown; including: a main discharge CCSCR device and an RC auxiliary trigger detection circuit; where,

[0025] The main discharge CCSCR device includes:

[0026]p-type silicon substrate 110; the well region formed on the p-type substrate 110, the well region includes a p-type well region 130 and an n-type well region 140, the two well regions are adjacent; the p A p-type heavily doped region 131, an n-type heavily doped region 132, and an n-type heavily doped region 133 are provided in the well region 130; a p-type heavily doped region 140 is provided in the n-type well region region 141, a p-type heavily doped region 142 and an n-type heavily doped region 143; a gate oxide layer is arranged on the silico...

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Abstract

The invention belongs to the field of electronic technology, and specifically relates to the design of an electrostatic discharge (ESD) protection circuit, and specifically provides a three-terminal compact composite SCR device (CCSCR) for full-chip ESD protection, including a main discharge CCSCR device and an RC auxiliary Trigger detection circuit; the main discharge CCSCR device is a three-terminal device, which introduces three parasitic SCR paths on the basis of the CMOS device structure, so as to achieve highly robust full-chip ESD protection in a smaller layout area; RC auxiliary trigger detection The introduction of the circuit can further reduce the trigger voltage of the device; in addition, the CCSCR device of the present invention can also be used as a two-terminal device to provide ESD protection between any IO port and the power supply.

Description

technical field [0001] The invention belongs to the field of electronic technology, and in particular relates to the design of an electrostatic discharge (Electro-Static discharge, ESD for short) protection circuit, especially a silicon controlled rectifier SCR (Silicon Controlled Rectifier for short SCR) used for full-chip ESD protection. Background technique [0002] In the process of semiconductor chip manufacturing, packaging and transportation, and user use, ESD phenomena are ubiquitous; the instantaneous high-voltage electrostatic pulse generated by ESD can flow into the chip through the pins of the chip, causing gate oxide breakdown and damage to the internal circuit of the chip. unable to work properly. In recent years, with the rapid development of the electronics industry, the line width of integrated circuits has been further reduced, the integration level of chips has been further increased, and the gate oxide layer of MOSFET devices has become thinner and thinne...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/02
CPCH01L27/0248H01L27/0266
Inventor 刘志伟董小雨刘继芝
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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