Method and device for writing multi-channel FIFO in parallel

Abstract

The invention provides a method for writing multi-channel FIFO in parallel. The method comprises the steps that S1, receiving multi-channel data from multiple channels at the same time; S2, respectively splicing the data input by each channel, and respectively registering the spliced data according to the channels when the spliced data reaches a preset quantity; and S3, dividing the data storage module into a plurality of independent areas according to the number of channels of the plurality of channels, enabling each independent area to correspond to one channel, respectively writing the dataspliced and registered for each channel into the independent area corresponding to the channel, and performing state marking on the writing state of the channel. According to the invention, bit widthconversion of the data is realized outside the RAM in the multi-channel FIFO, and polling and writing are carried out on a plurality of channels by utilizing bit width conversion time, so that read-write interruption caused by accumulation of the data in the processes of splicing, writing and reading is avoided, and the read-write efficiency of the multi-channel FIFO is greatly improved.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a method for realizing parallel writing into multi-channel FIFOs. Background technique [0002] In the field of digital integrated circuit design, storage components are an indispensable part of most designs. Storage components include RAM, ROM, FIFO, CAM, etc., among which FIFO (First-In-First-Out) is an extremely important storage Components, which use a first-in-first-out policy in the data buffering process, can store data sequentially and output data in the same order. FIFO has the characteristics of flexibility, convenience, and high efficiency. It is often used for buffering data streams, data streams crossing clock domains, and data bit width conversion. It is widely used in FPGA design. [0003] At present, in the design, the processing of parallel multi-channel FIFO generally uses the IP core wizard to generate multiple FIFOs, and assigns a FIFO to each cha...

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Problems solved by technology

[0005] In order to overcome the problem of excessive resource consumption in multi-channel FIFOs, the present invention proposes a method for writing in parallel to multi-channel FIFOs, the method is used to store data received simultaneously from multiple channels in a data storage module, so The methods described include:

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