Array substrate, display device and driving method thereof

Abstract

The embodiment of the invention provides an array substrate, a display device and a driving methodthereof. The array substrate comprises a substrate, a plurality of scanning lines and a plurality of data lines. The plurality of scanning lines and the plurality of data lines are arranged in a crossed manner to form a plurality of pixel units which are arranged in an array manner. At least one row of pixel units corresponds to two scanning lines, and the two scanning lines corresponding to the same row of pixel units synchronously receive scanning signals. According to the array substrate, the two scanning lines are arranged on the same row of pixel units, the number of the electrically connected pixel units on each scanning line is reduced, then the resistance and capacitance delay on the scanning lines is reduced, and the charging time of the grid electrode is guaranteed. Moreover, the two scanning lines corresponding to the pixel units in the same row synchronously receive scanning signals, so that the grid electrodes of the pixel units in the same row are enabled to be synchronously opened, and the normal display of images is realized.

Description

technical field [0001] The present invention relates to the technical field of liquid crystal display, in particular to an array substrate display device and a driving method thereof. Background technique [0002] With the development of TV industry technology, people have higher and higher requirements for the quality of liquid crystal display, and the resolution of liquid crystal display panel is also higher and higher. At present, 4K2K (ie UHD: 3840x2160) TV has become the mainstream of the market, and the market share The resolution is getting higher and higher, and the development of products with a higher resolution of 8K4K (7680x4320) is also in progress. [0003] There is RC Delay (resistor-capacitance delay) at each position of a scan line, so the gate open states of the pixel units on the same scan line are also different. The RC Delay near the gate drive circuit side is small, and the gate drive The RC delay on the circuit side is large. For an 8K4K LCD panel, t...

AI Technical Summary

Problems solved by technology

For an 8K4K LCD panel, there are 4320 scanning lines and 23040 data lines in its driving architecture. The theoretical charging time of each row of pixels is only 3.7uS. If the RC delay is large, the charging time of the pixels may be too short and the gate It cannot be fully opened, which will affect the transmission of the driving signal and cause uneven display of the screen

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