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Interrupt system for RISC-V architecture

A RISC-V, a series of technologies, applied in the address formation of the next instruction, multi-program device, instrument, etc., can solve the problems of slow saving speed, low efficiency of interrupt subroutine entry, etc., and achieve the effect of shortening the time

Pending Publication Date: 2019-07-12
NUCLEI SYST TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in the interrupt mechanism of CLIC, the storage speed of mcause and mepc is slow, and the efficiency of jumping to the corresponding interrupt subroutine entry is low.

Method used

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  • Interrupt system for RISC-V architecture
  • Interrupt system for RISC-V architecture
  • Interrupt system for RISC-V architecture

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Embodiment Construction

[0056] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention.

[0057] The present invention provides an interrupt system for RISC-V architecture. Its working principle is to reduce the number of instructions to run by adding registers or changing some instructions, so as to improve the speed of saving the value in the register and shorten the jump to the corresponding Interrupt the time of subroutine entry to improve efficiency.

[0058] The present invention will be described in further detail below in conjunction with examples and specific implementation methods.

[0059] An interrupt system for RISC-V architecture, the system includes: mstatus register, medeleg register, mideleg register, mie register, mtvec register, mtvt register, mscratch register, mepc register, mcause register, mtval register, mip register, mnxti register, mintst...

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Abstract

The invention discloses an interrupt system for an RISC-V architecture. The system comprises an original register in a CLIC, and further comprises a pushmcause register, a pushmepc register, an interrupt response register and an mtvt2 register. The pushmcause register is used for storing the value in the mcause into a stack through an instruction. The pushmepc register is used for storing the value in the mepc into a stack through an instruction. The interrupt response register is used for responding to a non-vector interrupt request sent by the CLIC through an instruction, obtaining an interrupt subprogram entry address and modifying global interrupt enabling. The mtvt2 register is used for storing the base address of the non-vector interruption in the CLIC mode, and the number of runninginstructions is reduced by increasing the register or changing part of the instructions, so that the purposes of increasing the value storage speed in the register, shortening the time of jumping tothe entrance of the corresponding interruption subprogram and improving the efficiency are achieved.

Description

technical field [0001] The invention relates to the technical field of low power consumption kernel interrupt processing, in particular to an interrupt system for RISC-V architecture. Background technique [0002] Interrupt mechanism (Interrupt), that is, the processor core is suddenly interrupted by other requests in the process of sequentially executing the program instruction flow and suspends the execution of the current program, and turns to process other things. After it finishes processing other things, then Return to the point where the previous program was interrupted and continue to execute the previous program instruction flow. Among them, the "other request" that interrupts the processor's execution of the program instruction flow is called an interrupt request (Interrupt Request), and the source of the interrupt request is called an interrupt source (Interrupt Source). Usually, the interrupt source is mainly from peripheral hardware devices. And the processor ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/32G06F9/30
CPCG06F9/327G06F9/30098G06F9/4831G06F2209/481G06F9/30101G06F9/30076G06F13/26G06F13/24G06F9/4812G06F9/48
Inventor 胡振波
Owner NUCLEI SYST TECH
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