Verification method and verification platform based on computing unit

Abstract

The invention relates to the technical field of electronics, in particular to a verification method and a verification platform based on a computing unit, and the method comprises the steps: obtaininga to-be-verified instruction; calling an operation code sequence, an operand sequence and a register sequence in a virtual sequence library according to the to-be-verified instruction so as to construct verification excitation; capturing the verification excitation by using a monitor, and sending the verification excitation into a reference model; and comparing and checking the calculation unit processing result collected by the monitor and the output structure of the reference model by using a scoring plate to obtain a verification result. By calling the operand sequence, the operand sequence and the register sequence in the virtual sequence library, the complex sequence is divided and combined, and the verification efficiency of the to-be-verified method is improved.

Description

technical field [0001] The invention relates to the field of electronic technology, in particular to a verification method and a verification platform based on a computing unit. Background technique [0002] UVM is a verification platform development framework based on the SystemVerilog class library. Verification engineers can use its reusable components to build a functional verification environment with standardized hierarchical structures and interfaces. The UVM verification methodology effectively combines methods such as test stimulus random generation, self-test bench and randomization constraints. It adopts the best framework to achieve coverage-driven verification, enabling verification engineers to reduce risks by adopting advanced verification techniques. [0003] In processor design, many corresponding computing units are designed according to its instruction set, such as simple fixed / floating point computing unit, complex fixed / floating point computing unit, dat...

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Problems solved by technology

[0003] In processor design, many corresponding computing units are designed according to its instruction set, such as simple fixed / floating point computing unit, complex fixed / floating point computing unit, data replacement unit, fixed / floating point conversion unit, division / square root Unit, evaluation unit, encryption and decryption unit and other computing units; various computing instructions have different operand types, initial state register configuration, immediate data, types of registers to be fed back, abnormal conditions, and result checking methods and other scenarios are different; The existing traditional verification methods are to build their own verification environments through various computing units. The verification methods are different, which is not conducive to unified management and affects verification efficiency.

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