self-adaptive high-speed SAR-ADC conversion time complete utilization circuit and method

Abstract

The invention discloses a self-adaptive high-speed SAR-ADC conversion time complete utilization circuit and method. According to the circuit and method for completely utilizing the ADC conversion time, when an ADC enters a maintaining mode, clk _ vcm rises, a trigger DFF1 outputs the sum of the last control bit of a resistor R1 and a control bit needing to be adjusted to the control bit of the current resistor R1, and it is guaranteed that the current comparison frequency is equal to n; the counter is reset after the rising edge of the clk _ vcm is delayed; After entering the comparison mode,the counter counts the current comparison times; For an nbit ADC with redundancy, n times of comparison needs to be carried out, and if m times of comparison are carried out in the previous time, thecurrently needed comparison frequency is Yn = Y (n-1) + m-n. According to the method, the comparison times are counted, and then the comparison times are adjusted in a self-adaptive mode, so that theADC carries out accurate n times of comparison in the whole conversion period, and the conversion error is reduced. Under the condition that the ADC conversion rate is changed, real-time tracking canbe realized, and the conversion rate is improved; In addition, the method is irrelevant to process, power supply voltage and temperature changes and is high in reliability.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to an adaptive high-speed SAR-ADC conversion circuit and a method for fully utilizing the conversion time. Background technique [0002] For the commonly used SAR-ADC sampling, the hold and each comparison are driven by an external synchronous clock to nbit SAR-ADC without redundancy. If the sampling rate is Fs, sampling and hold each take up 1 clock cycle, and n comparisons take up For n clock cycles, the ADC clock is at least (n+2)*Fs, and for redundant ADCs, the clock frequency will be higher. For example, for a 20Msps ADC with redundant 17bit, the clock frequency needs to be (17+2)*20=580MHz. Usually, a phase-locked loop is required to generate such a high clock, which wastes significant area and power consumption, and increases design complexity. [0003] The conversion time of high-speed SAR-ADC is very short, and the complete utilization of the conversion time i...

AI Technical Summary

Problems solved by technology

Usually a phase-locked loop is required to generate such a high clock, which wastes significant area and power consumption and increases design complexity

[0003] The conversion time of high-speed SAR-ADC is very short, and the complete utilization of the conversion time is very critical. If the phase-locked loop is not used, the asynchronous ultra-high-speed comparison clock generated inside the commonly used ADC varies greatly with the process, power supply voltage and temperature, resulting in ADC conversion. The time cannot be fully utilized, reducing the speed and accuracy of the ADC

At the same time, the traditional rc calibration method of comparing time cannot satisfy the full utilization of conversion time under various conversion rates

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