A standard cell library layout design rule verification method

Abstract

The invention provides a standard cell library layout design rule verification method. The method comprises the steps that path information of a standard cell library is extracted; Searching all standard units in the standard unit library, and generating a preparation list file; Providing a design rule configuration file, and formulating a design rule checking file; Formulating a standard unit boundary design rule and a corresponding standard unit boundary design rule check file; Automatically generating a unit layout design rule check file according to the preparation list file, the design rule check file and the standard unit boundary design rule check file; Standard units and unit layout design rule inspection files corresponding to the standard units are searched for, and program commands are executed to verify the standard units; And generating a standard unit result file and generating a standard unit library design rule inspection report. According to the method, the layout violation design rule after standard unit splicing is avoided. Therefore, rapid, efficient and accurate design rule inspection and verification of the standard cell library are realized.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to a method for verifying standard cell library layout design rules. Background technique [0002] The standard cell library is the basis of VLSI automatic design, and the optimized standard cell library can automatically carry out logic synthesis and layout layout and routing to improve design efficiency. The overall design process of the standard cell library includes: 1) The definition of the cell library and the determination of its characteristics, and the technical indicators of the cell library are determined according to the purpose and process of the cell library; 2) The circuit design of the standard cell, according to the technical indicators of speed and power consumption Design the device size of the inverter with unit drive capability according to the requirements, and design the device size of other standard cells according to the requirements of the transisto...

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Problems solved by technology

[0007] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a standard cell library layout design rule verification method, which is used to solve the problem of the need to perform DRC verification unit by unit in the prior art, which consumes a lot of development energy and is caused by a large number of standard units. Stitching generates new graphics that violate design rules, and errors are reported, resulting in low design efficiency

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