Method for improving precision of positioning defects on chip to graphic layer

Abstract

The invention discloses a method for improving precision of positioning defects on chip to a graphic layer. The method comprises the steps of: adding minimal repeated complete unit information to a silicon wafer according to a defect result observed by electron beam scanning; and reassigning coordinates to each defect according to the setting of an original point of an original complete unit of the minimal repeated complete unit, so as to improve the positioning of subsequent silicon wafer with the graphic layer. The method can automatically add the minimal repeated complete unit information,and improve the precision of positioning the defects in the bare wafer to later wafers with graphic layers.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuits, in particular to a method for improving the positioning accuracy of a defect on an optical sheet to a graphic layer. Background technique [0002] In the production process of large-scale integrated circuit wafers, it is necessary to detect defects in different processes in a timely manner. The common method is to scan the bright field and dark field. There is no graphics, and the entire silicon wafer is regarded as a complete unit with the smallest repetition. When the electron beam scans to observe the defects, the silicon wafer is aligned according to the notch and the crystal edge used for marking on the silicon wafer, and the silicon wafer wafer with the normal pattern layer has the smallest repeated complete unit information. When observing defects by electron beam scanning, the positioning is carried out according to the cross marks in the silicon wafer. There is a certain...

AI Technical Summary

Problems solved by technology

When observing defects by electron beam scanning, the positioning is carried out according to the cross marks in the silicon wafer. There is a certain displacement deviation between the two positioning systems, so the defects on the optical wafers are inaccurately positioned to the subsequent fixed-point electron beam scanning observation defects on silicon wafers with pattern layers. The problem of small size defects cannot be accurately judged, which will affect the subsequent graphics.

Evaluation of Factors That Seriously Affect Defects on Wafer Yield

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