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Radiation Hardened D-Latch

A latch and anti-irradiation technology, which is applied in the field of anti-radiation reinforcement, can solve the problems of poor anti-double-node flipping ability, long delay time, and multiple hardware, and achieve high reliability, reduced delay, and small size.

Active Publication Date: 2022-03-22
ZHONGBEI UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The present invention aims to solve the problem that the traditional anti-radiation D latch needs more hardware, high power consumption, long delay time, and although it can realize anti-double-node flipping, it has poor anti-dual-node flipping ability, and even cannot realize double-node flipping. For the fault tolerance problem of node flipping, the present invention provides an anti-irradiation D latch

Method used

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Embodiment Construction

[0054] Next, the technical solutions in the embodiments of the present invention will be described in connection with the drawings of the embodiments of the present invention, and it is understood that the described embodiments are merely the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative labor are in the range of the present invention.

[0055] It should be noted that the features of the present invention in the present invention may be combined with each other in the case of an unable conflict.

[0056] The present invention will be further described below with reference to the accompanying drawings and specific examples, but is not limited as the invention.

[0057] See figure 1 In the present embodiment, the anti-irradiation D latch described in the present embodiment includes NMOS transistors N1 to N16, PMOS transis...

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Abstract

The anti-radiation D latch belongs to the field of anti-nuclear reinforcement in the reliability of integrated circuits. Solve the problem that the traditional radiation-resistant D latch requires more hardware, high power consumption, long delay time, and although it can realize anti-double-node flipping, it has poor anti-double-node flipping ability, and even cannot realize the fault tolerance to double-node flipping. It includes NMOS transistors N1 to N16, PMOS transistors P1 to P16 and two inverters I1 and I2, and uses few devices, small size and simple structure, thereby reducing the power consumption of the entire latch and having low hardware overhead. The signal at the input terminal of the latch can be transmitted to the output port through only one transmission gate, the data transmission time is short, and it can also realize the fault tolerance to any single-node and double-node flipping, so as to realize the fault-tolerant protection against single-node and double-node flipping. The invention can provide protection for the application of integrated circuit chips in high-radiation environments (such as aerospace and ground nuclear power plants, etc.).

Description

Technical field [0001] The present invention belongs to the field of radiation radiation reinforcement in the reliability of integrated circuits. Background technique [0002] In the digital integrated circuit, the D latch can be used to constitute a timing circuit such as a trigger, a register, and is one of the important components of a digital integrated circuit. Therefore, its reliability is critical. The D latch has the function of saving the data. Once the saved data receives an error, it will affect the correctness of the subsequent circuit function, so it is necessary to refractory reinforcement of the D latch. The traditional anti-radiation D latch generally uses three mode redundancy to reinforcement, the disadvantage is that the required hardware (up to 102 transistors), high power consumption, long delay time, and although the anti-double node flip can be achieved. However, there is poor ability to flip in anti-double nodes, and even fail tolerance with two nodes flip...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K19/003
CPCH03K19/003
Inventor 郭靖
Owner ZHONGBEI UNIV
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