Operator mapping method and system for coarse-grained reconfigurable architecture

Abstract

The invention provides an operator mapping method and a system of a coarse-grained reconfigurable architecture, comprises a data flow graph generating step, a minimum cycle start interval calculatingstep, an operator scheduling step, a scheduling judging step, an array graph constructing step, a sorting step, a forward mapping step, a current mapping judging step, a reverse tracing step, all mapping judging steps and a configuration generating step. The invention can achieve better mapping performance in shorter compiling time, obtain higher acceleration ratio, and has smaller area and energyconsumption overhead. The ordered operator nodes are mapped forward in turn. When the forward mapping fails, a new mapping path is entered by reverse backtracking, and a successful mapping scheme isfound as far as possible without degrading the performance.

Description

technical field [0001] The invention relates to the field of computer compilers, in particular to an operator mapping method and system of a coarse-grained reconfigurable architecture. Background technique [0002] A typical application of a coarse-grained reconfigurable architecture is to speed up the execution of the innermost loop. The compiler extracts the operators of the loop body to build a data dependency graph, and then maps it to the coarse-grained PE array to execute the loop body in a soft pipeline. The machine cycle between two loops is called loop start interval II (II, Initiation Interval). The smaller the II, the faster the loop execution speed and the better the acceleration performance. One of the indicators to measure the quality of the compiler is the mapped II, and the other is the compilation time. [0003] The existing REGIMap method first constructs a compatibility graph between the data flow graph and the time-expanded PE (Process Element) array gr...

AI Technical Summary

Problems solved by technology

This method based on subgraph matching has a large search space and long compilation time

Moreover, using this method requires adding a certain number of registers to the PE, and the addition of a large number of registers will increase power consumption and area overhead.

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