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A bridge device for multi-channel low-speed peripheral integration

A bridging device and bridging technology, applied in the field of digital circuit front-end design, to achieve the effect of reducing circuit board area, strong adaptability, stable and reliable data transmission

Active Publication Date: 2021-11-16
TIANJIN JINHANG COMP TECH RES INST
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The present invention proposes a bridge device for the integration of multi-channel low-speed peripherals to solve the problem of synchronizing cross-clock domain behavior between multi-channel serial port logic and external low-speed devices

Method used

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  • A bridge device for multi-channel low-speed peripheral integration
  • A bridge device for multi-channel low-speed peripheral integration

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Embodiment Construction

[0017] In order to make the purpose, content and advantages of the present invention clearer, the specific implementation manners of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments.

[0018] This embodiment proposes a bridge device for the integration of multiple low-speed peripherals that integrates six serial ports and four CAN controllers. Its architecture is as follows figure 1 shown. The bridge device includes a synchronous bridge unit and an expandable peripheral interface unit. Wherein, the synchronous bridge unit is a bidirectional interface unit, and the interface on one side realizes the connection with the external expansion interface of the processor; the interface on the other side realizes the connection with the extensible peripheral interface. The processor can use the synchronous expansion method, and use any clock within 100MHz to realize the interconnection with the synchronous br...

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Abstract

The invention belongs to the technical field of front-end design of digital circuits, and in particular relates to a bridging device for integrating low-speed peripherals of multiple paths and used for expanding low-speed peripherals on the periphery of a processor. The invention can ensure stable and reliable data transmission from the external expansion interface of the higher-speed processor to the low-speed external equipment. Compared with the solution of using discrete components, the invention can greatly reduce the area of ​​the circuit board, achieve the purpose of reducing the cost, and also provide convenience for logic debugging and use. In the application process, the present invention can conveniently provide users with extended settings, conveniently increase or decrease the amount of logically used resources according to actual usage conditions, and has good adaptability. In addition, the extensible peripheral units in the present invention can also be used in cascade to construct a two-level address mapping relationship, and have strong adaptability to designs with less address space. When the bandwidth and FPGA resources allow, it can provide a processor peripheral interface and any multiple low-speed peripheral devices to realize cross-clock domain synchronization processing.

Description

technical field [0001] The invention belongs to the technical field of front-end design of digital circuits, and in particular relates to a bridging device for integrating low-speed peripherals of multiple paths, which is applied to expand low-speed peripherals on the periphery of a processor. Background technique [0002] In the field of industrial control, low-speed communication interfaces such as serial ports and CAN are commonly used command and data transmission channels. In a whole machine system, usually multiple serial ports and CAN are integrated on a host node or relay node. These control systems are usually used in the embedded field, and are installed in the chassis by means of line cards. The size of the line card is small, and when the traditional serial port control chip and CAN interface control chip are used to realize, the area of ​​the board card will be insufficient. By integrating an FPGA chip with a suitable capacity on the periphery of the processor...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/44
CPCG06F9/44
Inventor 鲁毅付彦淇赵斌王旭何全
Owner TIANJIN JINHANG COMP TECH RES INST
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