Fast interrupt control system and method for risc-v architecture

Abstract

The invention discloses a fast interrupt control system and method for RISC-V architecture, comprising: a pocket, an interrupt source priority register, an interrupt wait register, a priority threshold register, a priority judgment module, an interrupt enable register, Interrupt response register, interrupt completion register and EIP register. Each interrupt source corresponds to an interrupt source priority register. The priority threshold register stores the priority threshold of the interrupt target; the priority judging module compares the priority of the interrupt source and the interrupt target; the interrupt enable register stores the state value of the shielded interrupt source. A fast interrupt control system is set between the source and the interrupt target to control the sending of interrupt requests, so as to solve the problem of realizing the interrupt nesting mechanism in the RISC‑V architecture.

Description

technical field [0001] The invention relates to the technical field of low power consumption kernel interrupt processing, in particular to a fast interrupt control system and method for RISC-V architecture. Background technique [0002] Interrupt mechanism (Interrupt), that is, the processor core is suddenly interrupted by other requests in the process of sequentially executing the program instruction flow and suspends the execution of the current program, and turns to process other things. After it finishes processing other things, then Return to the point where the previous program was interrupted and continue to execute the previous program instruction flow. Among them, the "other request" that interrupts the processor's execution of the program instruction flow is called an interrupt request (Interrupt Request), and the source of the interrupt request is called an interrupt source (Interrupt Source). Usually, the interrupt source is mainly from peripheral hardware devic...

AI Technical Summary

Problems solved by technology

However, due to the default hardware mechanism of the RISC-V architecture, in the processor of the RISC-V architecture, neither the hardware nesting mechanism of the ARM architecture nor the second-level interrupt nesting mechanism of the 8051 is available, so it cannot pass the ARM Architecture and technical solution of 8051 single-chip microcomputer realize the problem of RISC-V architecture interrupt nesting mechanism, and the interrupt efficiency is poor

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