Stacked embedded package structure and manufacturing method thereof

Abstract

The present invention discloses a stacked embedded package structure and a manufacturing method thereof. The package structure includes a package substrate, a first chip, a second chip, and a plurality of interconnection structures; the package substrate is provided with an upper substrate surface and a lower substrate surface which are arranged oppositely; the package substrate has a chamber; thefirst chip is disposed in the chamber; the first lower surface of the first chip is provided with a plurality of first electrodes; the second chip is disposed on the package substrate; the second lower surface of the second chip is provided with a plurality of second electrodes; the plurality of interconnection structures are used for conductively connecting the plurality of first electrodes andthe plurality of second electrodes; and a part of the interconnection structures pass through the first chip so as to conductively connect the first electrodes. According to the stacked embedded package structure and the manufacturing method thereof of the invention, the packaging technology is utilized to package the two different chips on the same package substrate, and therefore, multi-chip high integration can be realized, and the utilization ratio of the package substrate can be improved; and the packaging processing of semiconductor chip packaging and a semiconductor package body is completed at the package substrate, and therefore, complicated and cumbersome standards and process docking of the semiconductor chip packaging and the semiconductor package body can be omitted, the circulation and transfer of electronic manufacturing can be decreased, manpower and material resources can be saved, and the cost of electronic products can be further reduced.

Description

Technical field [0001] The invention relates to the field of semiconductor packaging, in particular to a stacked embedded packaging structure and a manufacturing method thereof. Background technique [0002] Stacked semiconductor chip packaging is an important 3D packaging form to realize miniature high-density system-in-a-package, which is beneficial to improve the package integration and package device performance. [0003] Currently, the industry has the following main structures and process methods to realize stacked chip interconnection: [0004] (1) First complete the multi-layer stacking of bare chips, and then perform related multi-chip electrical interconnection by means of leads to complete the basic stacked chip system interconnection; [0005] (2) The assembly of semiconductor packaged devices on circuit boards is usually completed by surface mount technology. [0006] The shortcomings of the above-mentioned existing processes are: (1) The docking standards and processes be...

AI Technical Summary

Problems solved by technology

[0006] The disadvantages of the above-mentioned existing processes are: (1) the docking standards and processes between the semiconductor electronic package and the semiconductor package device are complex and cumbersome; (2) on the surface mount, the semiconductor package device is usually connected by solder Electrical interconnection with the circuit board; (3) The current surface mount solder connection requires a large pad and pad spacing of the semiconductor package device, such as the pad / spacing is 280 microns / 400 microns, which is not precise enough, and the solder The connection requires more complex solder reflow process control; (4) The semiconductor packaging device is assembled on the circuit board by surface mount method. Due to the increase in the area of ​​the semiconductor packaging device, it will occupy a larger surface area of ​​the circuit board, hindering the semiconductor package. Miniaturization of packaged device assembly

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