A fast reconfiguration method of hardware compression core based on dsp

Abstract

A fast reconfiguration method based on a DSP-based hardware compression core, the method is applied to a fast reconfiguration device, the fast reconfiguration device includes DSP, CIS and FPGA, an image acquisition circuit is constructed on the FPGA, and the image acquisition circuit Comprise hardware compression kernel, it is characterized in that: it comprises the following steps: (1) construct the logical layer based on UART agreement of hardware compression kernel on FPGA; Determine the image type; (3) DSP sends image compression configuration information to the hardware compression core through the preset UART protocol according to the image type, and returns to step (2) to enter the configuration of the next image. The fast reconfiguration method of the DSP-based hardware compression core can deliver image compression configuration information in real time according to image characteristics.

Description

technical field [0001] The invention relates to the technical field of high-speed scanners, in particular to a fast reconfiguration method of a DSP-based hardware compression core. Background technique [0002] The digitization of paper documents plays an active role in improving the efficiency of e-government affairs and has become an important way to realize the digitization of government affairs. The contact image sensor (hereinafter referred to as CIS) scanner, because CIS itself is an optical system, does not need to add an additional optical system, has a simple structure, low cost, light and practical, and is very suitable for image scanning of paper documents. [0003] Spatial redundancy caused by the correlation between adjacent pixels in the image; temporal redundancy caused by the correlation between different frames in the image sequence; spectral redundancy caused by the correlation of different color planes or spectral bands. The purpose of data compression is...

AI Technical Summary

Problems solved by technology

However, the hardware compression kernel built by FPGA cannot use complex algorithms to judge the classification of scanned media, so it is difficult to dynamically and automatically adjust the image compression configuration information of the hardware compression kernel. The image compression configuration information of the hardware compression kernel is mainly the image compression ratio. When the image compression ratio of the core changes, the configuration information of the relevant registers of the control chip of the general control circuit will also change, such as the speed of paper feeding, etc.

The usual way is to send image compression configuration information on the PC side, but because the PC side itself has to deal with many tasks, and the PC side belongs to the upper layer protocol layer, it has to go through the middle layer of the protocol layer to reach the bottom layer protocol layer, so it is difficult to meet the requirements of image compression. Real-time requirements for scanning

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