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Method for automatically deleting invalid via holes in Cadence software

An automatic deletion and via technology, which is applied in CAD circuit design, special data processing applications, instruments, etc., can solve the problems of time consumption, huge workload, unsatisfactory results, etc., and achieve high work efficiency, Reduce workload and design reasonable effects

Inactive Publication Date: 2018-11-20
SHANDONG CHAOYUE DATA CONTROL ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The workload of layout design for a large PCB is quite huge. During the layout operation, there will inevitably be a large number of invalid vias. Simply relying on manual inspection will consume a lot of time and workload, and the results are often not ideal.

Method used

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Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0020] A method for automatically deleting invalid vias in Cadence software, the method steps are as follows:

[0021] Step 1) Modify the menu bar of Allegro software and add Skill to the menu bar;

[0022] Step 2) Modify the files in the directory, and add the above skill into the calling sequence;

[0023] Step 3) Put the file in the directory and execute the Delete Unconnected Via command in the menu bar to automatically delete invalid vias.

Embodiment 2

[0025] A method for automatically deleting invalid vias in Cadence software, the method steps are as follows:

[0026] Step 1) Modify the menu bar of the Allegro software and add Skill to the menu bar; the path of the configuration file allegro.men is C:\Cadence\SPB_16.6\share\pcb\text\cuimenus.

[0027] Step 2) Modify the allegro.ilinit file under the directory C:\Cadence\SPB_16.6\share\local\pcb\skill, and add the above skill to the calling sequence;

[0028] Step 3) Put the rm_nc_via.il file in the directory C:\Cadence\SPB_16.6\share\local\pcb\skill, and execute the Delete Unconnected Via command in the menu bar to automatically delete invalid vias.

Embodiment 3

[0030] A method for automatically deleting invalid vias in Cadence software, the method steps are as follows:

[0031] Step 1) Modify the menu bar of the Allegro software and add Skill to the menu bar; the path of the configuration file allegro.men is C:\Cadence\SPB_16.6\share\pcb\text\cuimenus; the configuration file allegro. Add the code in the corresponding position in the menu to add the corresponding item in the menu bar; after modifying the menu bar, add Delete Unconnected Via in the Check toolbar;

[0032] Step 2) Modify the allegro.ilinit file under the directory C:\Cadence\SPB_16.6\share\local\pcb\skill, and add the above skill to the calling sequence;

[0033] Step 3) Put the rm_nc_via.il file in the directory C:\Cadence\SPB_16.6\share\local\pcb\skill, and execute the Delete Unconnected Via command in the menu bar to automatically delete invalid vias.

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PUM

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Abstract

The invention discloses a method for automatically deleting invalid via holes in Cadence software. The method comprises the following steps of step 1, modifying a menu bar of Allegro software and adding Skill in the menu bar; step 2, modifying a file in a directory and adding the skill into a calling sequence; and step 3, placing the file in a directory and executing a Delete Unconnected Via command in the menu bar in order to automatically delete the invalid via holes. The method has the advantages of reasonable design, convenience for use, high working efficiency and the like, due to the fact that a Skill extension program loading interface is reserved in the CadenceAllegro software, a PCB design engineer can develop an extension function on the basis of original software by using an Allegro development language, the redundant via holes can be quickly positioned, manual deletion of reports is not needed, and a Layout engineer can quickly delete the invalid and redundant via holes through the Skill, so that the PCB design work efficiency is improved, and the workload of the PCB design engineer is effectively reduced.

Description

technical field [0001] The invention relates to the technical field of PCB Layout design, in particular to a method for automatically deleting invalid vias in Cadence software. Background technique [0002] In PCB Layout design, Layout engineers need to do a lot of layout and routing work, and it is easy to generate redundant operations and some redundant vias. These redundant via data will exist in the design file, which not only increases the size of the data file, but also affects the accuracy of the entire design file database. In severe cases, database errors may occur, causing the design file to be unusable. [0003] Before the design files are delivered for production, layout engineers need to remove all invalid and unconnected vias in the design files to reduce the short circuit risk of the finished PCB. The workload of layout design for a large PCB is quite huge. During the layout operation, there will inevitably be a large number of invalid vias. Simply relying on...

Claims

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Application Information

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IPC IPC(8): G06F17/50
CPCG06F30/39
Inventor 王增超刘泽李健
Owner SHANDONG CHAOYUE DATA CONTROL ELECTRONICS CO LTD
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