A lateral semiconductor device with a shallow trench isolation structure interlaced with interdigitated arrangement

Abstract

A lateral semiconductor device with an interdigitated shallow trench isolation structure, comprising: a P-type substrate, a high-voltage N-type region is arranged above the P-type substrate, and an N-type drift region is arranged above the high-voltage N-type region and a P-type body region, an N-type drain region and three shallow trench isolation regions are provided in the N-type drift region, an N-type source region and a P-type region are provided in the P-type body region, and a high-voltage N-type region is also provided A U-shaped gate oxide layer is provided, and the U-shaped opening of the gate oxide layer faces the drain end, and the two ends respectively extend to the top of the P-type body region and the top of the shallow trench isolation region, and a polysilicon gate is arranged above the gate oxide layer. The field plate is respectively provided with a drain metal contact, a source metal contact and a body metal contact on the upper surfaces of the N-type drain region, the N-type source region and the P-type region, and it is characterized in that the shallow trench isolation region is Arranged in a staggered interdigitated manner in the drift region. The structure of the invention can obtain lower on-resistance on the basis of constant breakdown voltage.

Description

technical field [0001] The invention relates to the field of power semiconductor devices, and relates to a lateral semiconductor device with an interdigitated shallow trench isolation structure. Background technique [0002] Lateral Double-Diffused MOSFET (LDMOS) has the advantages of high breakdown voltage, high input impedance and easy integration with other devices, and is widely used in high-voltage integrated circuits and power integrated circuits . Compared with traditional MOSFET devices, LDMOS devices have a low-doped drift region. When a high voltage is applied between the drain and source, the drift region is completely depleted, so it can withstand a higher voltage. [0003] In the design of the LDMOS device structure, shallow trench isolation technology (Shallow Trench Isolation, STI) is often used in the drift region to improve the withstand voltage capability of the device. The LDMOS device with STI structure, STI can bear most of the electric field in the dr...

AI Technical Summary

Problems solved by technology

Although this process can improve the withstand voltage capability of the device, the STI structure will increase the flow path of the current from the source to the drain, resulting in an increase in the on-resistance of the device.

Therefore, when the STI structure is used in the drift region of LDMOS, a better compromise between breakdown voltage and on-resistance cannot be achieved.

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