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Parallel-serial conversion circuit and device applied to high-speed interface physical layer chip

A physical layer chip and high-speed interface technology, applied in the field of high-speed parallel-to-serial conversion design, can solve the problems of internal noise differential signals prone to delay differences, complex circuits, etc., to achieve expanded application range, high-speed parallel-to-serial conversion, simple circuit Effect

Active Publication Date: 2022-08-09
SHENZHEN STATE MICROELECTRONICS CO LTD
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  • Claims
  • Application Information

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Problems solved by technology

[0003] The purpose of the present invention is to provide a parallel-to-serial conversion circuit and device applied to high-speed interface physical layer chips, aiming to solve the problems of complex circuits, easy generation of internal noise and delay in output differential signals in traditional technical solutions difference problem

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  • Parallel-serial conversion circuit and device applied to high-speed interface physical layer chip
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  • Parallel-serial conversion circuit and device applied to high-speed interface physical layer chip

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[0017] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention.

[0018] see Figure 1 to Figure 5 , an embodiment of the present invention provides a parallel-serial conversion circuit applied to a high-speed interface physical layer chip for converting parallel data into differential serial data. The parallel-serial conversion circuit includes: a phase-locked loop 10, a parallel data sampling unit 20. Data selection and distribution control unit 30 , first serial register 40 , second serial register 50 and differential serial data generating unit 60 .

[0019] It is worth noting that if figure 1 As shown in the figure, the embodiment of the present i...

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Abstract

The invention belongs to the technical field of high-speed parallel-serial conversion design, and provides a parallel-serial conversion circuit applied to a high-speed interface physical layer chip, comprising: a phase-locked loop, a parallel data sampling unit, a data selection and distribution control unit, a first serial A row register, a second serial register, and a differential serial data generating unit. According to the first clock and the second clock, the parallel data sampling unit is used to sample the parallel data to generate the odd-numbered parallel data and the even-numbered parallel data, and the odd-numbered parallel data and the even-numbered parallel data are converted by the data selection and distribution control unit into The odd-numbered serial data and the even-numbered serial data are processed by the differential serial data generating unit, and the differential serial data is finally output. Using the design method of pure digital circuit, through the circuit structure design of parity circuit, the internal frequency of the chip is reduced, and the IP multiplexing of the parallel-serial conversion circuit of the high-speed interface physical layer under different processes can be better realized.

Description

technical field [0001] The invention belongs to the technical field of high-speed parallel-serial conversion design, and in particular relates to a parallel-serial conversion circuit and device applied to a high-speed interface physical layer chip. Background technique [0002] At present, high-speed interfaces are used more and more widely, and the physical layer interfaces of many protocols (such as PCIe, USB, SATA, SRIO, etc.) are implemented by serializer-deserializer (Serializer-Deserializer, SerDes) technology. However, the realization of the physical layer of the high-speed interface has always been a difficult problem in the design of the industry due to the need to design a mixed circuit of digital and analog. As an important part of SerDes circuit design, parallel-serial conversion circuit is used to transmit serialized differential data. Its design quality will directly affect the performance of the SerDes sending port. Most of the existing parallel-serial conve...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M9/00
CPCH03M9/00Y02D10/00
Inventor 邱钧华谢文刚吴志远高新军陈柳明
Owner SHENZHEN STATE MICROELECTRONICS CO LTD
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