Techniques to reduce read-modify-write overhead in hybrid dram/nand memory

Abstract

A method of choosing a cache line of a plurality of cache lines of data for eviction from a frontend memory is provided. The method includes steps: assigning a baseline replacement score to each way of a plurality of ways of a cache, the ways respectively storing the cache lines; assigning a validity score to each way based on a degree of validity of the cache line stored in each way; assigning aneviction decision score to each way based on a function of the baseline replacement score for the way and the validity score for the way; and choosing a cache line of the way having a highest eviction decision score as the cache line for eviction.

Description

technical field [0001] Some embodiments of the present disclosure relate generally to memory device structures, and to methods of memory device management. Background technique [0002] In the field of memory storage, data centers storing large amounts of memory try to achieve high capacity, high performance, low power usage, and low cost. Flash memory may be a viable candidate for data centers because it can provide high capacity and efficient power usage at a reduced cost compared to dynamic random access memory (DRAM). Flash memory, for example, is capable of delivering gigabytes of storage capacity per module, 10 times the capacity achievable using DRAM technology. Also, flash memory uses lower standby power. [0003] Unfortunately, flash memory generally offers weaker performance compared to DRAM, while also having more limited endurance. For example, certain types of flash memory (eg, ZNAND) may have significantly longer latencies for read and write operations than ...

AI Technical Summary

Problems solved by technology

For example, certain types of flash memory (eg, ZNAND) may have significantly longer latency for read and write operations than can be achieved using DRAM technology

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