Data circular buffering method and device used for SOCFPGA, storage medium and terminal

Abstract

The invention discloses a data circular buffering method and device used for SOCFPGA, a storage medium and a terminal. The method includes the steps that according to a data write-in sequence of data,the data is written into n buffers in sequence, wherein n is a positive integer and is determined according to buffering depth; according to the newest write-in position and the final reading position, effective buffers are determined, wherein the effective buffers are the buffers, which store unread data, in the n buffers; when the data is read, the data stored in the effective buffers is read in sequence according to the data reading sequence from the final reading position until the newest write-in position is reached. In the provided scheme, the data processing efficiency of a system canbe effectively improved.

Description

technical field [0001] The invention relates to the technical field of data processing, in particular to a data circular buffering method and device, a storage medium, and a terminal for SOCFPGA. Background technique [0002] Due to the integrated processor and Field Programmable Gate Array (Field Programmable Gate Array, referred to as FPGA) architecture, compared with traditional devices, System on Chip Field Programmable Gate Array (System on Chip FPGA, referred to as SOCFPGA) devices have higher The advantages of higher integration, lower power consumption, smaller circuit board area, and higher bandwidth communication between processor and FPGA. [0003] Taking the Extensible Processing Platform (ZYNQ) as an example, it is an FPGA solution with a system-on-a-chip enhanced RISC Machines (ARM for short). The ZYNQ can not only have the real-time and parallel characteristics of FPGA, but also can start the system on ARM to provide rich functions. [0004] Among them, FPGA...

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Problems solved by technology

[0005] Therefore, the communication speed between FPGA and ARM determines the data processing efficiency of the SOCFPGA system to a large extent, and none of the existing solutions can provide a more reasonable processing logic and cannot effectively solve the problem of data processing between FPGA and ARM. The problem that the data processing efficiency of the system based on low-configuration programmable devices (such as low-configuration ZYNQ) is affected due to the mismatch of processing speed

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