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Delta-Sigma modulator and signal conversion method

一种三角积分、调变器的技术，应用在模转换、代码转换、模/数转换等方向，能够解决错误、降低最终输出数据准确性等问题，达到降低额外回路延迟的影响的效果

Active Publication Date: 2018-06-08
REALTEK SEMICON CORP
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  • Abstract
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, as the frequency of the clock signal and the operating speed of the circuit become faster and faster, the extra loop delay (excess loop delay) inside the delta-sigma modulator will cause the delta-sigma modulator to make errors when sampling the input signal, reducing the Accuracy of final output data

Method used

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  • Delta-Sigma modulator and signal conversion method
  • Delta-Sigma modulator and signal conversion method

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Embodiment Construction

[0011] The following is a detailed description of the embodiments in conjunction with the accompanying drawings, but the provided embodiments are not used to limit the scope of the present invention, and the description of the structure and operation is not used to limit the sequence of execution, any recombination of components The structure and the devices with equivalent functions are all within the scope of the present invention. In addition, the drawings are for illustrative purposes only and are not drawn to original scale. For ease of understanding, the same components will be described with the same symbols in the following description.

[0012] The terms "first", "second", etc. used herein are not intended to refer to the order or sequence, nor are they used to limit the present invention. They are only used to distinguish components or components described with the same technical terms. Operation only.

[0013] As used herein, "about", "approximately" or "approxima...

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Abstract

The invention relates to a Delta-Sigma modulator and a signal conversion method. The Delta-Sigma modulator comprises a Delta-Sigma modulation loop and a plurality of adjusting loops. The Delta-Sigma modulation loop processes an input signal based on a clock signal and adjusts the signal to generate a quantitative output signal, wherein the clock signal has a clock period. The Delta-Sigma modulation loop has a first delay time equivalent to M clock periods, M being integer multiple of 0.5 and larger than 1. The plurality of adjusting loops delay a plurality of second delay times of the quantitative output signal to generate adjusting signals.

Description

technical field [0001] This case relates to an integrated circuit, and in particular to a delta-sigma modulator with a mechanism for adjusting loop delay and its signal conversion method. Background technique [0002] The delta-sigma modulator is often used in high-resolution analog-to-digital converters because of its characteristics such as noise frequency shifting. However, as the frequency of the clock signal and the operating speed of the circuit become faster and faster, the extra loop delay (excess loop delay) inside the delta-sigma modulator will cause the delta-sigma modulator to make errors when sampling the input signal, reducing the The accuracy of the final output data. Contents of the invention [0003] In order to solve the above problems, an aspect of the present application is to provide a delta-sigma modulator, which includes a delta-sigma modulation loop and a plurality of adjustment loops. The delta-sigma modulation loop processes the input signal and...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M3/00
CPCH03M3/412H03M1/742H03M3/37H03M3/454H03M3/464H03M3/494
Inventor 周晓波
Owner REALTEK SEMICON CORP
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